Integrated Circuit Redundant Wire Resistance Mitigation
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Solution Overview
Problem
In advanced process nodes, the increased metal resistance and via resistance of narrower metal wires lead to performance and reliability issues, particularly due to electromigration, which limits the scalability of metal wires and vias in physical design.
Innovation Solution
The implementation of a specific cell layout with redundant parallel output wires and redundant routing paths reduces output net resistance and electromigration sensitivity by splitting current flow between multiple conductive paths, thereby improving circuit performance and manufacturing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If metal wire width is decreased to scale down, then area is reduced, but resistance increases
Solution Approach 1:
The patent divides the current path into multiple parallel metal wires instead of using a single narrow wire. By segmenting the current flow across multiple wires (e.g., two or more parallel wires), the total resistance is reduced while maintaining a compact area. Each wire carries a portion of the total current, effectively lowering the resistance without requiring each individual wire to be wider.
2Area of moving object
If metal wire width is decreased to scale down, then area is reduced, but electromigration sensitivity increases
Solution Approach 1:
The patent segments the current flow into multiple parallel paths using multiple metal wires. This distribution of current across multiple wires reduces the current density in each individual wire, thereby reducing electromigration sensitivity. The segmentation principle allows the design to maintain small wire widths while avoiding electromigration issues through parallel current distribution.
3Area of moving object
If via size is decreased to scale down, then area is reduced, but via resistance increases
Solution Approach 1:
The patent uses multiple parallel metal wires that require multiple vias to connect to upper or lower metal layers. By distributing the connection across multiple vias instead of using a single large via, the total via resistance is reduced. Each via carries a portion of the current, effectively lowering the overall resistance while maintaining small via sizes consistent with scaled-down processes.
4Device complexity
If unidirectional routing is enforced for output pin M1, then routing complexity is reduced, but resistance increases due to longer current path
Solution Approach 1:
The patent segments the output connection into multiple parallel metal wires (M1, M1R, etc.) that can be routed in different directions. This segmentation allows the current to flow through multiple parallel paths, reducing the effective resistance of the output net. While each individual wire may follow routing constraints, the parallel configuration provides multiple paths that collectively reduce resistance without requiring complex multi-directional routing for a single wire.
Data Source
AI summary
Various implementations described herein are directed to an integrated circuit with mitigated resistance. The integrated circuit may include a cell having a plurality of transistors including a first transistor of a first type and a second transistor of a second type that is different from the first type. The integrated circuit may include a first wire coupling the first transistor to the second transistor. The integrated circuit may include a second wire coupling the first wire to an output routing wire. The integrated circuit may include a redundant wire further coupling the first wire to the output routing wire.