IC Register Dump Access Using Privilege Level Indicators
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Solution Overview
Problem
Existing integrated circuit (IC) register dump methods risk revealing sensitive information, posing security vulnerabilities by allowing unauthorized access to confidential data.
Innovation Solution
Implementing hardware-implemented Privilege Level Indicators (PLIs) to control access to IC registers, ensuring only permitted values are output during a secure memory dump operation, using a processor with an Instruction Set Architecture (ISA) to check and manage privilege levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional scan-based DFT is used for register dump, then debuggability is maintained, but security vulnerabilities arise allowing unauthorized access to confidential data
Solution Approach 1:
The patent segments the register dump operation into two distinct privilege levels: secure mode and debug mode. The Privilege Level Indicator (PLI) mechanism divides the register access space into protected segments (secure registers) and accessible segments (non-secure registers). This segmentation allows the system to maintain security for sensitive data while still enabling debuggability for non-sensitive registers through the same scan infrastructure.
Solution Approach 2:
The Privilege Level Indicator (PLI) acts as an intermediary mechanism between the scan input and the register contents. The PLI is inserted into the scan path and mediates access by comparing the privilege level of the accessing entity with the required privilege level for each register. This intermediary enables conditional access control without requiring complete redesign of the scan architecture.
2Reliability
If security measures are added to protect scan dump, then security is improved, but device complexity increases
Solution Approach 1:
The Privilege Level Indicator (PLI) mechanism serves multiple functions simultaneously: it provides security protection for sensitive registers, enables debuggability for non-sensitive registers, and integrates with the existing scan infrastructure. The same PLI mechanism handles both security enforcement and debug access control, eliminating the need for separate complex security and debug architectures.
Solution Approach 2:
The patent introduces a new parameter (privilege level) to the existing scan architecture to enable security control. By adding the PLI parameter that can take different values (secure mode or debug mode), the system can dynamically control access without changing the fundamental scan architecture. This parameter-based approach allows flexible security configuration without requiring complex hardware modifications.
Data Source
AI summary
A device includes multiple registers, multiple hardware-implemented Privilege Level Indicators (PLIs), and one or more circuits. The registers are to store respective values. The PLIs are to specify privilege levels for accessing the respective registers. The one or more circuits are to perform a secure memory dump operation including (i) checking the PLIs of one or more of the registers and (ii) outputting the values of the registers that are permitted for outputting according to the respective PLIs.