IC Register Reset for DFT Mode Security
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Solution Overview
Problem
Existing methods for securing digital information on integrated circuits (ICs) during test modes, such as Design-for-Test (DFT) mode, are inadequate as they either reduce test coverage, are error-prone, or can be reverse-engineered, failing to effectively protect encryption keys and other secret information from unauthorized access.
Innovation Solution
The proposed solution involves configuring ICs to enter a test mode, resetting registers, configuring them into scan chains, and using test control logic to manage access, including writing known bit patterns to RAM and providing benign outputs for secret information locations, thereby preventing unauthorized access during DFT operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If secret-bearing registers are excluded from the DFT process to protect secret information, then information security is improved, but test coverage is reduced and IC yield decreases
Solution Approach 1:
The patent applies preliminary action by resetting all registers to a known state before DFT mode activation and clearing RAM contents before test operations. This proactive measure ensures secret information is erased before potential exposure during testing, while still allowing comprehensive test coverage of all circuit components including previously excluded registers.
Solution Approach 2:
The patent changes the temporal state of memory contents by introducing time-based control: registers are reset to known states at specific times (before DFT mode), and RAM is cleared at specific moments (before test operations). This parameter change approach allows full test coverage while ensuring secret information is not exposed during testing.
2Reliability
If manual identification and removal of secret-bearing registers is implemented, then information security is improved, but the process becomes error-prone and complex
Solution Approach 1:
The patent applies universality by implementing a comprehensive register reset mechanism that handles all registers uniformly without requiring manual identification of secret-bearing ones. The same reset infrastructure serves both functional operation and DFT protection, eliminating the need for separate identification and removal processes.
Solution Approach 2:
The system performs self-service by automatically resetting all registers to known states before DFT mode activation without requiring designer intervention to identify which registers contain secret information. This automated approach eliminates manual errors while maintaining information security.
3Reliability
If obfuscation techniques are used to protect register contents, then information security is improved, but specialized DFT algorithms are required that are not supported by industry-standard CAD tools
Solution Approach 1:
The patent extracts the security function from complex obfuscation algorithms and implements it through simple, standardized register reset operations. By removing secret information from registers before DFT mode rather than hiding it through complex algorithms, the solution maintains compatibility with industry-standard CAD tools and manufacturing processes.
4Reliability
If comprehensive register reset before DFT mode is implemented, then information security is improved, but additional control logic and time are required
Solution Approach 1:
The patent merges the register reset operation with the existing DFT mode activation sequence. The reset control logic is integrated into the same control infrastructure that manages DFT mode transitions, combining security functionality with existing operational workflows to minimize additional time requirements.
Data Source
AI summary
The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Transitory secrets are secured whether stored in registers or latches, RAM, and/or permanent secrets stored in ROM and/or PROM. One embodiment for securing information on an IC includes entering a test mode and resetting each register in response to entering the test mode of operation and prior to receiving a test mode command. An integrated circuit embodiment includes a test control logic operative to configure the integrated circuit into a test mode and to control the integrated circuit while in the test mode, a set of registers, and a functional reset controller coupled to the test control logic and to the set of registers, operative to receive a reset command from the test control logic and provide the reset command to the set of registers in response to a command to enter the test mode.