Integrated Circuit Reset Extension for Low-Voltage Standby Blocks

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Solution Overview

Problem

Integrated circuits face challenges in resetting portions that are supplied with voltages between the first and second voltage levels, specifically between 0.66V and 0.9V, where the second voltage is insufficient for resetting, leading to incomplete reset operations.

Innovation Solution

The integrated circuit design includes a first portion with a reset input and an activation module that activates a second portion, which emits a replicated reset signal until a threshold time has elapsed, ensuring the second portion is fully reset, even when the initial reset signal is received during a standby mode.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If a second supply voltage less than the first voltage is used to retain information in memory, then energy consumption is reduced, but the resetting function becomes insufficient or fails

Engineering Contradiction:
Improveenergy consumptionVSAvoidresetting function
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The patent introduces a voltage boosting circuit as an intermediary component between the low-voltage memory portion and the reset logic. This circuit temporarily boosts the supply voltage from the second voltage level to the first voltage level during reset operations, enabling the reset function to operate reliably even when the memory portion runs on lower voltage for energy savings. The intermediary circuit resolves the contradiction by providing voltage enhancement only when needed for resetting, without requiring the entire system to operate at higher voltage continuously.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Use of energy by stationary object

If the supply voltage is lowered to the second voltage level for standby mode, then power consumption decreases, but the reset signal becomes ineffective in resetting the circuit portion

Engineering Contradiction:
Improvepower consumptionVSAvoidreset operation
Core Design Contradiction:
Use of energy by stationary objectVSEase of operation

Solution Approach 1:

The patent implements dynamic voltage adjustment where the supply voltage to the memory portion is adaptively changed based on operational requirements. During normal standby operation, the voltage remains at the lower second level to minimize power consumption. However, when a reset operation is detected or required, the voltage is dynamically boosted to the first level to ensure proper reset functionality. This dynamic switching resolves the contradiction between low power consumption and effective reset operation.

Inventive Principle:
Principle #15Dynamics

3Measurement precision

If a reset signal is sent to a portion supplied by voltage between 0.66V and 0.9V, then the reset signal is received, but the portion is not properly reset

Engineering Contradiction:
Improvereset signal receptionVSAvoidreset completion
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent changes the voltage parameter dynamically during the reset process. When a reset signal is received at the lower voltage level (0.66V-0.9V), the system detects this condition and automatically adjusts the supply voltage upward to the first voltage level (above 0.9V) to complete the reset operation successfully. This parameter change ensures that the reset logic receives sufficient voltage to properly reset the circuit, even though the memory portion operates at lower voltage for power savings. The resolution maintains reliable reset completion while preserving energy-efficient operation during normal states.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11550377B2Integrated circuit, method for resetting and computer program product
Publication Date: 2023.01.10 STMICROELECTRONICS (ROUSSET) SAS
  • US11550377B2 patent drawing
  • US11550377B2 patent drawing
  • US11550377B2 patent drawing

AI summary

Integrated circuit, method for resetting and computer program product. The integrated circuit comprises a first portion and a second portion. The first portion comprises a reset input configured to receive a reset signal, an activation module connected to the reset input. The activation module is configured to activate the second portion upon reception of the reset signal. The first portion comprises an emissions module configured to emit a replicated reset signal. The second portion can be selectively activated or deactivated. The second portion comprises a reset input configured to receive the replicated reset signal of the emissions module, a determination module configured to determine that an elapsed time starting from the activation of the second portion of the circuit oversteps a threshold.