IC Reset Signal Replication for Low-Voltage Sleep Domains
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Solution Overview
Problem
Integrated circuits face challenges in resetting parts that are powered by voltages between 0.66V and 0.9V, as existing methods are insufficient to allow for proper reset operations in this voltage range.
Innovation Solution
An integrated circuit design that includes a first part with a reset input and an activation module to activate a second part, which transmits a replicated reset signal until a threshold time has elapsed, ensuring the second part can be reset even when initially powered by insufficient voltage for reset.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a second supply voltage lower than the first voltage is used to power a part of the integrated circuit, then power consumption is reduced and the circuit can operate in sleep mode, but this voltage may be insufficient to allow the part to be reset
Solution Approach 1:
The first part is activated in advance to generate and transmit the replicated reset signal before the second part is fully powered up. This preliminary action ensures that the reset signal is available when the second part reaches a voltage level capable of responding to it, resolving the contradiction between low-power operation and reset capability.
Solution Approach 2:
The first part acts as an intermediary that generates the replicated reset signal based on the external reset signal received during standby mode. This intermediary function allows the reset operation to be initiated at a lower voltage threshold while ensuring proper reset execution when the second part is powered, bridging the gap between sleep mode voltage constraints and reset requirements.
2Loss of energy
If the second part is kept in standby mode to save power, then energy consumption is reduced, but the reset signal received during standby mode cannot properly reset the second part
Solution Approach 1:
The system performs preliminary capture of the external reset signal by the first part while the second part is in standby mode. The replicated reset signal is held ready and automatically transmitted when the second part is activated, ensuring reset functionality is maintained without requiring the second part to be continuously powered.
Solution Approach 2:
The first part creates a copy (replicated reset signal) of the external reset signal. This copied signal is then transmitted to the second part at the appropriate time when voltage levels are sufficient, allowing the reset operation to be decoupled from the power state of the second part and enabling both power savings and proper reset operation.
3Speed
If the reset signal is transmitted immediately upon reception, then the reset operation is fast, but the signal may not be properly received if the second part is in standby mode with insufficient voltage
Solution Approach 1:
The external reset signal is captured and replicated in advance by the first part while the second part is still in standby mode. The replicated signal is then transmitted immediately upon activation of the second part, combining the benefits of early signal capture with timely transmission at optimal voltage levels.
Solution Approach 2:
The first part serves as an intermediary buffer that receives and holds the external reset signal, then transmits it as a replicated signal when conditions are optimal. This intermediary approach maintains fast reset response while ensuring reliable signal reception by the second part at appropriate voltage levels.
Data Source
Figure 1~2
Figure 3~4
AI summary
Integrated circuit (IC) reset method and computer program output. The integrated circuit (IC) comprises a first part (PART1) and a second part (PART2). The first part (PART1) includes a reset input (11A) configured to receive a reset signal (RST1), and an enable module (ACTIV) connected to the reset input (11A). The enable module (ACTIV) is configured to activate the second part (PART2) upon receiving the reset signal (RST1). The first part (PART1) includes a transmit module (EMI) configured to transmit a replicated reset signal (RST2). The second part (PART2) can be selectively activated or deactivated.The second part (PART2) includes a reset input (14B) configured to receive the replicated reset signal (RST2) from the transmitter module (EMI), a determination module (DET) configured to determine that a time elapsed since the activation of the second part (PART2) of the circuit exceeds a threshold.