IC Resistor Cell Layout Without Extra Mask Steps

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Solution Overview

Problem

Existing methods for integrating resistors into integrated circuit (IC) devices require additional masks, increasing manufacturing time, cost, and complexity, especially when using high density metal-inter (MIM) structures.

Innovation Solution

Incorporating resistor structures partially by active regions of the IC device without requiring additional masks, utilizing through via structures and metal layers to electrically couple the resistor with other circuit elements, and configuring adjacent transistors to be in an always-OFF state or with floating gate regions to manage parasitic capacitances.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional MIM resistor structures are used, then high density and precision are achieved, but additional masks are required increasing manufacturing time, cost, and complexity

Engineering Contradiction:
Improveresistor precisionVSAvoidmanufacturing complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges the resistor structure with the active region by forming the resistor within the same semiconductor layer without requiring separate masking steps. The resistor is created as an integrated part of the active region formation process, combining what were previously separate fabrication steps into one unified process.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The active region serves multiple functions: it acts as both the functional semiconductor region and as the resistor structure. This multi-functionality eliminates the need for dedicated resistor fabrication steps and masks, reducing manufacturing complexity while maintaining precision.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Manufacturing precision

If additional masks are used for resistor integration, then manufacturing precision is maintained, but manufacturing time and cost increase

Engineering Contradiction:
Improvelayout precisionVSAvoidmanufacturing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The resistor structure is prepared simultaneously with the active region during the same fabrication step, rather than adding it later. This preliminary integration approach maintains layout precision while eliminating the time required for subsequent masking and patterning operations.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If resistor structures are integrated without additional masks, then manufacturing complexity is reduced, but control over parasitic capacitances becomes more challenging

Engineering Contradiction:
Improvemanufacturing complexityVSAvoidparasitic capacitance control
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies different configurations locally within the active region to manage parasitic capacitances. By adjusting the geometry, doping, or structure of specific portions of the integrated resistor, parasitic effects can be controlled at local levels without requiring additional masks or complex global processing steps.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250336834A1Integrated circuit device layout, system and method
Publication Date: 2025.10.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250336834A1 patent drawing
  • US20250336834A1 patent drawing
  • US20250336834A1 patent drawing

AI summary

Based on whether terminal ends of a resistor of an IC device are on a first or a second side, a resistor cell is selected from a cell library. Based on a resistance of the resistor, a number of instances of the selected resistor cell and/or one or more connections between the instances of the selected resistor cell is determined. Based on the determined number of the instances and/or one or more connections therebetween, a place-and-route operation is performed to obtain the layout for the IC device. The resistor cell includes a first resistor structure which has a first end in a first metal layer on the first side, a second end in a second metal layer on the second side, and a first active region between the first metal layer and the second metal layer and electrically coupled to the first end and the second end.