Integrated Circuit Resistors with Doped Silicon
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Solution Overview
Problem
The scaling down of semiconductor integrated circuits leads to increased complexity and high power dissipation, necessitating the development of low power dissipation devices like CMOS with metal gate electrodes and high-k dielectric materials, while maintaining precise resistance control in integrated circuits.
Innovation Solution
The method involves forming integrated circuits with a gate-last high-K metal gate fabrication process, where a doped silicon layer is used for resistors without a work-function metallic layer, and a silicide region can be optionally formed to adjust resistance, ensuring precise resistance control through in-situ and implantation doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scaling down is implemented to increase functional density, then productivity and production efficiency are improved, but power dissipation increases and manufacturing complexity increases
Solution Approach 1:
The patent changes the material parameters of the gate electrode from traditional silicon to metal materials, and the gate dielectric from conventional materials to high-k dielectric materials. This parameter change enables lower operating voltages and reduced power dissipation in scaled-down devices while maintaining the increased functional density achieved through scaling.
2Loss of energy
If metal gate electrodes and high-k dielectric are used to reduce power dissipation, then energy efficiency is improved, but device complexity and processing complexity increase
Solution Approach 1:
The patent segments the gate structure into distinct functional layers: a metal gate electrode layer and a high-k dielectric layer. This segmentation allows each layer to be optimized independently for its specific function while simplifying the overall processing by treating them as separate fabrication steps rather than integrated complex structures.
Solution Approach 2:
The patent applies preliminary doping to the semiconductor layer before forming the gate structure. This preliminary action prepares the semiconductor layer with appropriate electrical properties in advance, reducing the need for complex post-processing adjustments and simplifying the overall fabrication process of the metal gate device.
3Area of stationary object
If scaling down is implemented, then area is reduced and functional density is improved, but resistance control precision deteriorates
Solution Approach 1:
The patent changes the electrical parameters of the semiconductor layer through controlled doping, adjusting carrier concentration and mobility to achieve precise resistance values. This parameter control through doping compensates for the reduced physical dimensions, allowing precise resistance control even in miniaturized devices with smaller areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the fabrication of integrated circuits with reduced resistance variation and improved precision, addressing the challenge of high power dissipation and complexity in scaled-down semiconductor devices.
Implementation Method 1
in-situ and implantation doping
Implementation Method 2
resistance control
Data Source
AI summary
An integrated circuit includes a transistor. The transistor includes a first gate dielectric structure over a substrate, a work-function layer over the first gate dielectric structure, a conductive layer over the work-function layer, and a source/drain (S/D) region adjacent to each sidewall of the first gate dielectric structure. Additionally, the integrated circuit includes a resistor structure. The resistor structure further includes a first doped semiconductor layer over the substrate, wherein a top surface of the resistor structure is substantially planar with a top surface of the transistor.