IC Resource Sharing via Acceleration Function Table Routing
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Solution Overview
Problem
Conventional hardware acceleration frameworks in virtualized computing environments do not allow applications running in different virtual entities to share functions on the same integrated circuit (IC), leading to the need for additional hardware and increased time to route data between separate ICs for combined functions like machine learning and video transcoding.
Innovation Solution
An integrated circuit (IC) infrastructure that enables multiple tenants to share resources concurrently by partitioning the programmable IC into secure areas, allowing simultaneous access and processing of packets from different virtual entities using an acceleration function table to route packets to appropriate function circuit blocks and queue results based on packet handling data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware acceleration cards operate as single tenant devices, then security and dedicated performance are improved, but resource utilization and efficiency deteriorate
Solution Approach 1:
The hardware acceleration card is segmented into multiple isolated execution environments or tenants. Each tenant receives packets and processes them through dedicated function circuit blocks, with results queued separately. This segmentation allows multiple tenants to share the same physical hardware while maintaining security isolation, thereby improving resource utilization without compromising security
Solution Approach 2:
The hardware acceleration card is designed to serve multiple tenants simultaneously rather than being dedicated to a single tenant. The card can process packets from different tenants through the same function circuit blocks, making the hardware universal and multi-functional. This increases resource utilization while maintaining dedicated performance for each tenant through logical isolation
2Adaptability or versatility
If separate ICs are used for different functions, then functional specialization is improved, but device complexity and routing time increase
Solution Approach 1:
Multiple function circuit blocks that would traditionally require separate ICs are merged into a single hardware acceleration card. The card can dynamically route packets from different tenants to appropriate function circuit blocks internally, eliminating the need for external routing between separate ICs. This reduces device complexity and routing time while maintaining functional specialization through internal circuit block design
3Adaptability or versatility
If separate ICs are used for different functions, then functional capability is improved, but data routing time increases
Solution Approach 1:
Multiple function circuit blocks are combined within a single IC, allowing packets to be routed internally between different functions without leaving the chip. This internal routing eliminates the external data transmission delays that would occur when using separate ICs, thereby reducing routing time while maintaining diverse functional capabilities
Solution Approach 2:
An internal routing mechanism or switch fabric acts as an intermediary within the single IC to direct packets between different function circuit blocks. This internal mediator enables fast, low-latency routing between functions compared to external routing, reducing the time loss associated with data transmission between separate ICs
Data Source
AI summary
Sharing integrated circuit (IC) resources can include receiving, within a communication endpoint of an IC, a plurality of packets from a plurality of different source virtual entities, determining packet handling data for each packet of the plurality of packets using an acceleration function table stored within the IC, routing each packet of the plurality of packets to one or more selected function circuit blocks of a plurality of function circuit blocks in the IC based on the packet handling data of each respective packet, and processing the plurality of packets using the one more selected function circuit blocks generating a plurality of results corresponding to respective ones of the plurality of packets. The plurality of results are queued within the communication endpoint. Each result is queued based on the packet handling data of the corresponding packet.