Integrated Circuit Retiming Selective Flip-Flop Modeling
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Solution Overview
Problem
Conventional register retiming algorithms face challenges in handling complex flip-flops with secondary signals, leading to substantial area overhead and poor circuit performance due to the need for unnecessary modeling and gate-level combinational logic creation.
Innovation Solution
Implement selective modeling of complex flip-flops with heterogeneous secondary signals using a predetermined precedence scheme to create minimal gate-level models, allowing for comparable flip-flops to be retimed while retaining overlapping secondary signals, thereby reducing the number of retiming steps and area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If complete modeling of complex flip-flops with secondary signals is performed, then retiming operation can be executed, but huge area penalties and circuit performance degradation occur
Solution Approach 1:
The patent extracts only the essential secondary signals needed for retiming operation while leaving out redundant ones. By identifying and retaining only the critical secondary signals (such as clock enable) that affect retiming decisions, the method avoids complete modeling of all secondary signals, thereby reducing area overhead while maintaining retiming functionality.
Solution Approach 2:
The patent applies partial action by performing selective modeling of only necessary secondary signals rather than complete modeling. This partial approach focuses on the minimal subset of secondary signals that impact retiming, avoiding the excessive area cost of modeling all secondary signals while still enabling effective retiming operations.
2Extent of automation
If complete modeling of complex flip-flops is performed, then retiming can be executed, but the number of additional LUTs and flip-flops increases significantly
Solution Approach 1:
The patent extracts and retains only the essential secondary signals required for retiming, excluding redundant ones. This extraction approach reduces the number of additional LUTs and flip-flops needed by focusing only on critical signals that affect retiming decisions, thereby reducing device complexity while maintaining retiming capability.
Solution Approach 2:
The patent changes the parameter of secondary signal modeling from complete to selective. By modifying which secondary signals are modeled (only those essential for retiming), the method reduces the number of additional logic resources required, thus lowering device complexity while preserving retiming functionality.
3Area of stationary object
If selective modeling is performed on heterogeneous complex flip-flops, then area overhead is reduced, but compatibility of retiming operations must be maintained
Solution Approach 1:
The patent applies universality by creating a standardized approach to selective modeling that works across heterogeneous complex flip-flops with different secondary signals. The method identifies a common subset of essential secondary signals that can be uniformly modeled across different flip-flop types, enabling compatible retiming operations while reducing area overhead.
Solution Approach 2:
The patent applies local quality by tailoring the selective modeling to the specific secondary signals present in each heterogeneous flip-flop while maintaining a consistent framework. Each flip-flop is modeled with only its essential secondary signals relevant to retiming, allowing area optimization while preserving retiming compatibility across different flip-flop types.
Data Source
AI summary
An integrated circuit design may include registers and combinational logic. Integrated circuit design computing equipment may perform register retiming in the circuit design, whereby registers are moved across one or more portions of the combinational logic. The candidate registers to be retimed may have a different number or different types of secondary signals. In such scenarios, a selective modeling operation may be performed according to a predetermined precedence scheme to remove and model the differing secondary signals, thereby producing comparable registers with the same number and type of secondary signals. The comparable registers can then be retimed across the corresponding combinational logic. Backward or forward retiming operations may be performed in this way to achieve optimal circuit performance. During retiming adjacent combinational logic may also be combined to help minimize circuit area.