Integrated Circuit Reworking via Dry Etching and CMP
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Solution Overview
Problem
The fabrication of integrated circuit devices often results in defects during the formation of metal interconnections due to particle contamination, masking effects, or scratches, leading to reduced yield and potential discarding of wafers as scrap, which increases costs.
Innovation Solution
A reworking method involving sequential dry etching and chemical mechanical polish (CMP) processes to remove defective layers, allowing for the reforming of new base, dielectric, and cap layers, ensuring that integrated circuit devices can proceed to the next processing step without being discarded.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional deposition and etching processes are used to form metal interconnections, then the fabrication process can be completed, but defects such as particle contamination, masking effects, and scratches cause wafers to be discarded as scrap, reducing yield
Solution Approach 1:
The patent applies the discarding and recovering principle by systematically removing defective layers (base layer, dielectric layer, cap layer) through sequential dry etching and CMP processes, then reforming new layers to recover the wafer for continued processing. This transforms a defective structure into a recoverable state, preventing wafer scrap and improving yield while maintaining reliability through controlled layer removal and reforming
Solution Approach 2:
The patent implements preliminary action by performing inspection at multiple stages (after base layer formation, after dielectric layer formation, after cap layer formation) and immediately executing corrective reworking procedures when defects are detected. This early detection and intervention prevents defect propagation and enables timely recovery before the wafer reaches a scrap state, thereby improving both yield and reliability
2Productivity
If reworking processes (dry etching and CMP) are performed to remove defective layers, then wafer yield is improved by preventing scrap, but the fabrication process time and complexity increase
Solution Approach 1:
The patent applies segmentation by dividing the reworking process into distinct, modular stages: dry etching for selective layer removal, CMP for planarization and base layer removal, and reforming processes. Each stage addresses specific defect types and can be independently controlled and optimized. This segmented approach manages process complexity while enabling systematic defect correction to improve yield
Solution Approach 2:
The patent utilizes parameter changes by adjusting process conditions (etching parameters, CMP parameters, deposition parameters) based on the specific defect type and location detected during inspection. By dynamically changing process parameters rather than using fixed procedures, the reworking process can efficiently address diverse defects without requiring excessively complex process sequences, thereby improving yield while controlling complexity
3Reliability
If multiple sequential processes (deposition, etching, inspection, reworking) are performed to ensure defect-free metal interconnections, then reliability is improved, but manufacturing time and cost increase
Solution Approach 1:
The patent implements preliminary action through staged inspection points positioned after critical process steps (base layer formation, dielectric layer formation, cap layer formation). By inspecting early and executing reworking immediately when defects are detected, the process prevents defect propagation to subsequent steps, reducing the need for extensive rework later and minimizing total fabrication time while maintaining high reliability
Solution Approach 2:
The patent applies the skipping principle by enabling continuous processing flow through efficient reworking procedures. When defects are detected, the affected layers are rapidly removed and reforming is initiated without halting the entire fabrication line. This rushed-through approach to defect correction minimizes time loss compared to stopping for extensive analysis or complete process repetition, thereby maintaining reliability while reducing time penalties
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively removes defective layers, preventing integrated circuit devices from being scrapped and reducing costs by enabling the continuation of the fabrication process, thus maintaining yield and efficiency.
Implementation Method 1
performing a first dry etching to remove the first dielectric layer; performing a first dry etching process to remove the first cap layer
Implementation Method 2
performing a chemical mechanic polish (CMP) process to remove the first base layer
Data Source
AI summary
A reworking method for integrated circuit devices includes the following: providing a substrate having a first base layer and a first dielectric layer formed thereon, performing a first dry etching process to remove the first dielectric layer, performing a CMP process to remove the first base layer, and sequentially reforming a second base layer and a second dielectric layer on the substrate. When certain layers on the IC device have hailed an inspection or when quality defects are found, the defective layer is removed according to the provided reworking method.