IC Metal Routing Layout for Reduced Cell Pitch and Higher Gate Density
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Solution Overview
Problem
Existing integrated circuit (IC) designs face challenges in reducing the width and improving gate density due to limitations in routing and placement of conductive patterns.
Innovation Solution
Incorporating two-dimensional (2D) conductive patterns in metal layers, along with three or more consecutive vias in underlying via layers, to enhance routing efficiency and reduce cell pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional routing and placement methods are used, then routing connectivity is achieved, but cell pitch cannot be reduced and gate density remains limited
Solution Approach 1:
The patent introduces 2D conductive patterns in metal layers that extend in both horizontal and vertical directions, moving beyond conventional 1D linear routing. This dimensional expansion allows conductive patterns to route signals in two dimensions, enabling shorter pitch between gates while maintaining connectivity through vertical vias that connect different metal layers.
Solution Approach 2:
The patent implements a hierarchical structure where 2D conductive patterns in upper metal layers are connected to underlying via layers, which in turn connect to lower metal layers and gate structures. This nested arrangement of conductive patterns across multiple layers enables compact routing that reduces cell pitch while maintaining signal connectivity.
2Adaptability or versatility
If more conductive patterns are added to improve routing, then connectivity improves, but area utilization decreases
Solution Approach 1:
By extending conductive patterns in 2D within metal layers and utilizing vertical vias to connect multiple metal layers, the patent achieves enhanced routing flexibility without proportionally increasing cell area. The 2D patterns allow multiple routing paths to share the same footprint, improving adaptability while controlling area consumption.
Solution Approach 2:
The 2D conductive patterns serve multiple functions: they provide horizontal routing within metal layers, vertical connectivity through vias to other layers, and can be configured to support different circuit configurations. This multi-functionality allows a single conductive pattern structure to replace what would traditionally require multiple separate routing elements, improving versatility without increasing area.
Data Source
AI summary
An integrated circuit (IC) device includes a circuit region, a lower metal layer over the circuit region, and an upper metal layer over the lower metal layer. The lower metal layer includes a plurality of lower conductive patterns elongated along a first axis. The upper metal layer includes a plurality of upper conductive patterns elongated along a second axis transverse to the first axis. The plurality of upper conductive patterns includes at least one input or output configured to electrically couple the circuit region to external circuitry outside the circuit region. The upper metal layer further includes a first lateral upper conductive pattern contiguous with and projecting, along the first axis, from a first upper conductive pattern among the plurality of upper conductive patterns. The first lateral upper conductive pattern is over and electrically coupled to a first lower conductive pattern among the plurality of lower conductive patterns.