Integrated Circuit Routing with Dynamic Channel Compaction
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Solution Overview
Problem
Current electronic design automation tools face challenges in efficiently routing and compacting complex integrated circuit layouts, particularly in managing interconnects and optimizing space usage as feature sizes shrink and complexity increases.
Innovation Solution
The technique involves identifying cell rows and channels, determining net routing areas, using spine routing for nets spanning multiple rows or channels, and dynamically adjusting channel widths to minimize routing while ensuring connectivity and optimizing space usage through a computer-implemented system that automatically routes and compacts integrated circuit designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If automatic routing is used to connect inputs and outputs of devices, then routing efficiency is improved, but space utilization deteriorates due to insufficient compaction
Solution Approach 1:
The patent applies dynamics by making the routing process adaptive and iterative. The router dynamically adjusts routing paths based on available space, and the compactor iteratively modifies the layout to create better routing opportunities. This dynamic interaction between routing and compaction allows the system to efficiently route nets while continuously optimizing space utilization, resolving the contradiction between routing efficiency and space utilization.
Solution Approach 2:
The patent uses an intermediary approach by introducing a coordinated interaction between the routing algorithm and the compaction algorithm. Rather than treating them as separate sequential steps, the system allows them to work together iteratively, where each can influence and improve the other's results. This intermediary relationship enables the system to achieve both efficient routing and optimal space utilization simultaneously.
2Quantity of substance
If more devices are integrated on a single chip, then circuit complexity increases, but manufacturing precision requirements worsen
Solution Approach 1:
The patent applies segmentation by dividing the complex integrated circuit layout into manageable components such as cells, rows, and channels. This segmentation allows the routing and compaction algorithms to work on smaller, more manageable units while maintaining the overall circuit functionality. By breaking down the complex layout into structured segments, the system can achieve high device integration density while maintaining the manufacturing precision required for each individual feature.
3Area of stationary object
If channel width is reduced to optimize space, then area efficiency improves, but routing capability deteriorates
Solution Approach 1:
The patent applies dynamics by making channel widths adaptive rather than fixed. The compaction algorithm dynamically adjusts channel widths based on the actual routing requirements and available space. Channels are narrowed to the minimum width needed to accommodate the necessary interconnects, allowing the system to maximize area efficiency while maintaining adequate routing capability for all required connections.
Data Source
AI summary
An iterative technique is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying solid and hollow channels, the technique automatically places route paths to connect pins of cells in the solid channels, where route paths may be placed within the solid channels or hollow channels. The technique can reduce a width of at least one hollow channel when an entire space of the hollow channel is not occupied by a placed route path.