Hierarchical IC Routing via Flattened Layout Blockage Analysis
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Solution Overview
Problem
Current methods for routing integrated circuit designs are inefficient, particularly in hierarchical layouts, as they require excessive time and computational resources, and often result in unroutable designs due to inadequate consideration of metal layers across all levels of the hierarchy.
Innovation Solution
A method that flattens a 3D layout into a 2D layout, generates blockage information by categorizing temporary routes, and uses a depth-first search to establish a routing order, ensuring sufficient metal tracks are available at upper levels for automatic routing, with iterative corrections for unroutable sub-blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If automatic routers are run at each level of the circuit hierarchy separately, then routing speed is improved, but routability decreases due to inadequate consideration of metal layers across all levels
Solution Approach 1:
The patent divides the hierarchical routing problem into segments by processing levels in reverse order (lowest level first), where each level is routed separately using dedicated algorithms. This segmentation allows each sub-block to be routed independently with appropriate metal layer considerations, preventing resource conflicts while maintaining overall routability.
Solution Approach 2:
The patent performs preliminary routing actions at lower levels before proceeding to upper levels. By routing lowest-level sub-blocks first and reserving metal layers accordingly, the system ensures that upper-level routing has adequate resources available, preventing unroutable conditions while maintaining efficiency.
2Manufacturing precision
If physical synthesis is performed to optimize placement and timing, then design quality is improved, but turnaround time increases significantly
Solution Approach 1:
The patent segments the physical synthesis process into distinct phases: placement optimization, timing closure, and hierarchical routing. Each phase can be independently optimized and executed, allowing designers to perform comprehensive analysis where needed while avoiding redundant iterations, thus reducing overall turnaround time without sacrificing design quality.
3Reliability
If blockage patterns are set up to prevent router from using all metal layers at lower level cells, then routability is improved, but device complexity increases
Solution Approach 1:
The patent automatically performs preliminary metal layer reservation at each hierarchical level before routing begins. Blockage patterns are generated programmatically based on routing requirements and metal availability, eliminating the need for manual setup while ensuring proper resource allocation. This reduces routing complexity while maintaining routability.
Data Source
AI summary
An integrated circuit design is routed by first creating temporary routes in a flattened layout, generating blockage information for sub-blocks in the layout based on the temporary routes, and establishing a routing order for cells using a depth-first search. Cells in the original layout are then routed according to the routing order using the blockage information. The temporary routes are sorted into internal routes, terminal routes, and spanning routes. Blockage information for each sub-block includes a first cellview equal to the internal routes, a second cellview equal to the terminal routes plus the spanning routes, and a third cellview equal to the total tracks in the sub-block minus the first and second cellviews. The invention is particularly suited for routing a hierarchical integrated circuit design. By examining the complete hierarchy, the invention ensures that enough metal will be remaining at upper level sub-blocks to complete the routing automatically.