IC Routing Maze-Algorithm Single-Entry Partition Compliance
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Solution Overview
Problem
Conventional routing methods in integrated circuit design fail to guarantee single-entry-violation-free routing results due to their lack of partition awareness, often resulting in multiple entries into a single partition, which violates design and manufacturing constraints.
Innovation Solution
A computer-implemented method using a maze-routing approach that supports both feed-through and single-entry routing, which includes generating a routing wire network with feed-through ports across partitions, applying a partition boundary crossing checking procedure, and merging wire segments to ensure single-entry compliance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional routing methods are used, then routing speed is faster, but single-entry constraint violations occur due to lack of partition awareness
Solution Approach 1:
The routing process is segmented into two distinct phases: global routing that establishes partition-aware routing topology with single-entry compliance, and detailed routing that completes the interconnects. This segmentation allows the global routing phase to enforce partition constraints while the detailed routing phase handles the complex connection task, resolving the contradiction between constraint compliance and routing completion.
Solution Approach 2:
The global routing phase performs preliminary action by pre-establishing the routing topology and determining which nets require feed-through ports before detailed routing begins. This preliminary partition-aware planning ensures single-entry constraint compliance is built into the routing structure from the outset, preventing violations before they occur during the detailed routing completion phase.
2Manufacturing precision
If conventional routing methods are used, then routing complexity is lower, but multiple entries into single partition occur violating design constraints
Solution Approach 1:
A feed-through port mechanism is introduced as an intermediary element at partition boundaries. This mediator allows nets to pass through partitions in a controlled manner, ensuring single-entry compliance while maintaining routing flexibility. The feed-through port acts as a designated gateway that enforces the single-entry constraint without requiring complex real-time checking during detailed routing.
Solution Approach 2:
The routing method applies different qualities to different regions: partition-aware global routing is applied at the global level to establish topology and determine feed-through port locations, while conventional detailed routing is applied locally within partitions to complete connections. This local differentiation maintains manufacturing precision at the global constraint level while keeping local routing complexity manageable.
3Reliability
If partition-aware routing is implemented, then single-entry constraint compliance is achieved, but routing computation time increases
Solution Approach 1:
The computation is segmented into global routing computation that determines partition-aware topology and feed-through port locations, followed by detailed routing computation that completes connections using established paths. This segmentation concentrates the partition-aware computation in the global phase, preventing repeated constraint checking during detailed routing and reducing overall computation time while maintaining compliance.
Solution Approach 2:
Partition-aware routing information is computed preliminarily during global routing, including the identification of feed-through ports and the establishment of routing topology that satisfies single-entry constraints. This preliminary computation eliminates the need for repeated constraint verification during detailed routing, significantly reducing total computation time while ensuring constraint compliance is maintained throughout the process.
Data Source
AI summary
The present disclosure relates to a system and method for routing in an electronic circuit design. Embodiments may include providing, using a processor, a hierarchical electronic design having a plurality of partitions, at least one routing blockage, a source pin location, and one or more sink pin locations. Embodiments may also include generating a routing wire network configured to connect the source pin location and the one or more sink pin locations to create one or more segments, wherein generating the routing wire network includes creating two or more feed-through ports at one or more of the plurality of partitions. Embodiments may further include applying a maze-routing approach to each of the one or more segments of the routing wire network to form a routed net associated with the hierarchical electronic design.