IC Routing with Parasitic Constraint Estimation
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Solution Overview
Problem
Existing automatic routing techniques for integrated circuits fail to effectively manage parasitic issues such as capacitance, leading to increased signal coupling and performance issues, as they do not consider the impact of wiring parasitics during the routing process.
Innovation Solution
A constraint-driven automatic routing system that estimates parasitic values along the net path and uses these estimates to guide the routing process, ensuring compliance with timing and other performance requirements by rerouting if necessary, while considering parameters like propagation delay, capacitance, and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If automatic routing minimizes wire length to reduce space, then area utilization is improved, but parasitic capacitance increases leading to signal coupling and performance degradation
Solution Approach 1:
The router performs preliminary estimation of parasitic capacitance values along potential net paths before final routing is completed. This allows the routing algorithm to anticipate and avoid paths that would result in excessive capacitance, rather than dealing with the problem after routing is complete. The system calculates estimated capacitance values for different routing segments and uses these estimates to guide the routing decisions.
Solution Approach 2:
The routing system implements feedback by continuously monitoring estimated parasitic capacitance values during the routing process. When the estimated capacitance exceeds predefined thresholds or constraints, the system adjusts the routing path accordingly. This feedback mechanism allows the router to dynamically modify routing decisions based on real-time parasitic assessments, ensuring that performance requirements are met while maintaining efficient space utilization.
2Area of stationary object
If the router creates dense wiring patterns to minimize space, then area utilization is improved, but signal coupling (crosstalk) increases
Solution Approach 1:
The system performs preliminary assessment of potential signal coupling between adjacent wires during the routing planning phase. By estimating capacitance values for nearby net segments before finalizing the routing, the system can identify and avoid configurations that would lead to excessive crosstalk, even in dense wiring areas.
Solution Approach 2:
The router applies local quality control by adjusting routing parameters in specific high-risk areas. When dense wiring is necessary for area optimization, the system locally modifies routing paths or wire orientations in regions where signal coupling is likely to occur, based on estimated capacitance values. This allows selective mitigation of crosstalk in critical areas while maintaining overall density.
3Reliability
If the router removes existing wiring patterns to find better paths, then timing performance can be improved, but the process becomes inefficient if parasitic constraints are not considered
Solution Approach 1:
The system performs preliminary estimation of parasitic capacitance values for existing wiring patterns before deciding whether to rip-up and reroute. By calculating estimated capacitance values in advance, the router can identify which existing routes are likely to fail timing constraints and prioritize them for rerouting, rather than blindly removing and rerouting all wires. This preliminary assessment makes the rip-up and reroute process more targeted and efficient.
Solution Approach 2:
The routing system uses feedback from estimated parasitic capacitance measurements to guide the rip-up and reroute process. When timing constraints are violated, the system uses the pre-calculated capacitance estimates to identify the specific segments causing the problem and focuses rerouting efforts on those areas. This feedback-driven approach reduces unnecessary rerouting operations and improves overall routing efficiency while achieving timing closure.
Data Source
AI summary
A system of automatically routing interconnect of a integrated circuit design while taking into consideration the parasitic issues of the wiring as it is created. The system will be able to select an appropriate wiring pattern so that signals meet their performance requirements.