IC Routing for Retiming-Aware Register Placement
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Solution Overview
Problem
Current configuration methods for programmable integrated circuit devices do not adequately account for the availability of registers when retiming logic designs, leading to insufficient register capacity in critical paths and suboptimal performance.
Innovation Solution
A method that analyzes timing requirements and routes logic designs to incorporate storage elements, ensuring sufficient register availability for retiming by considering the distribution of pipeline registers and using latency-discovery retiming and enhanced retiming-aware routing techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If known configuration methods optimize circuit designs by detecting paths with longest delay and applying optimization techniques, then timing performance is improved, but register availability in critical paths becomes insufficient
Solution Approach 1:
The routing process is performed with advance knowledge of retiming requirements. The method pre-identifies critical paths and pre-allocates storage elements during routing before retiming occurs, ensuring that sufficient registers are available when retiming is applied to optimize timing performance.
Solution Approach 2:
The method uses timing analysis feedback from retiming-aware tools to guide the routing process. By detecting paths with longest delay and analyzing timing requirements, the routing algorithm can adjust its behavior to place storage elements in locations that will be most beneficial after retiming, creating a feedback loop between timing analysis and routing decisions.
2Speed
If logic designs are retimed by moving registers within the design, then higher clock speeds are achieved, but insufficient registers in some paths prevent effective retiming
Solution Approach 1:
Storage elements are pre-positioned during the routing phase based on predicted retiming needs. This preliminary action ensures that when retiming is subsequently applied to achieve higher clock speeds, the necessary registers are already in place and properly distributed throughout the design.
Solution Approach 2:
The method changes the routing parameters and cost functions to account for future retiming requirements. By modifying how the router evaluates potential paths and storage element placements, it optimizes for retiming capability rather than just initial timing, enabling better clock speed achievement.
3Device complexity
If routing is performed without considering future retiming requirements, then routing complexity is reduced, but timing optimization potential is lost
Solution Approach 1:
Timing requirements and retiming potential are analyzed in advance during the routing phase. This preliminary timing analysis allows the routing algorithm to make informed decisions about storage element placement without adding significant complexity, as the timing constraints are evaluated before final routing decisions are made.
Solution Approach 2:
The method introduces an intermediary routing-aware retiming tool that acts as a mediator between the routing process and final timing optimization. This intermediary analyzes timing requirements and provides feedback to the routing algorithm, enabling timing-optimized routing without requiring the router itself to be overly complex.
Data Source
AI summary
A method of configuring an integrated circuit device with a user logic design includes analyzing the user logic design to identify timing requirements of paths within the user logic design, determining latency requirements along those paths, routing the user logic design based on availability of storage elements for incorporation into those paths to satisfy the latency requirements, and retiming the user logic design following that routing by incorporating at least some of the storage elements.