IC Configuration Routing for Register-Aware Retiming
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Solution Overview
Problem
Existing configuration methods for programmable integrated circuit devices do not adequately account for the ability to retime designs by moving registers, leading to insufficient register availability in critical paths, which limits optimization and operability.
Innovation Solution
A method that analyzes user logic designs to identify timing requirements, routes the design based on storage element availability, and incorporates registers to satisfy latency needs, enabling effective retiming by modifying routing techniques to ensure sufficient register capacity where needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If known configuration methods optimize circuit designs by detecting paths with longest delay and applying optimization techniques, then delay reduction is achieved, but register availability in critical paths becomes insufficient
Solution Approach 1:
The routing process is performed in advance with knowledge of where registers will be needed for retiming. The method proactively routes logic to positions that will allow sufficient register availability in critical paths after retiming is applied, rather than reacting to register shortages after routing is complete.
Solution Approach 2:
The invention accounts for the dynamic nature of retiming by allowing the routing configuration to be optimized with the understanding that registers will be moved during retiming. The routing is not fixed but is planned to accommodate future register repositioning to meet timing requirements.
2Speed
If registers are moved forward in pipelined paths to retim the design, then clock speed is improved, but not all paths have enough registers available to support retiming
Solution Approach 1:
The routing is optimized locally in different regions of the circuit based on specific timing requirements. Critical paths are routed to ensure sufficient register availability, while non-critical paths may have different routing characteristics. Each region is configured with the appropriate register density needed for its specific timing constraints.
Solution Approach 2:
The routing process proactively identifies and prepares register resources in advance for paths that will require retiming. By analyzing timing requirements before final routing, the method ensures that sufficient registers are made available in critical paths before the retiming operation is performed.
3Device complexity
If routing is performed without considering future retiming needs, then routing complexity is reduced, but optimization potential is lost
Solution Approach 1:
Timing analysis and register requirement identification are performed in advance during the routing phase. This preliminary action allows the routing algorithm to incorporate retiming considerations without requiring complex post-routing adjustments, as the necessary register availability is established during the routing process itself.
Solution Approach 2:
The routing process incorporates feedback from timing analysis about where registers will be needed for optimal performance. This feedback loop allows the routing algorithm to adjust its decisions to ensure sufficient register availability in critical paths, improving overall optimization potential while maintaining manageable routing complexity.
Data Source
AI summary
A method of configuring an integrated circuit device with a user logic design includes analyzing the user logic design to identify timing requirements of paths within the user logic design, determining latency requirements along those paths, routing the user logic design based on availability of storage elements for incorporation into those paths to satisfy the latency requirements, and retiming the user logic design following that routing by incorporating at least some of the storage elements.