Semiconductor Component Routing Under IR Drop Resistance Limits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The performance of integrated circuits (ICs) is diminished by voltage drops due to parasitic resistance and capacitance after layout implementation, necessitating time-consuming adjustments and potential enlargement of the IC area to compensate.
Innovation Solution
A method involving pre-determined IR drop limits and iterative routing adjustments to control parasitic resistance within acceptable thresholds, reducing the performance gap between pre- and post-layout simulations without altering device size or placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If automatic placement and routing tools are used for IC layout, then layout implementation efficiency is improved, but parasitic resistance and capacitance in MEOL/BEOL cause voltage drops that diminish IC performance
Solution Approach 1:
The patent applies preliminary action by estimating parasitic resistance and capacitance values before final layout implementation. The system calculates IR drop and signal integrity issues in advance, allowing designers to optimize the layout before manufacturing, thus preventing performance degradation while maintaining efficient automated layout generation
Solution Approach 2:
The patent implements feedback by using post-layout simulation results to identify voltage drops and signal integrity problems, then feeding this information back to adjust the layout. This iterative process allows the system to refine the design based on actual parasitic effects, improving IC performance while maintaining layout efficiency
2Reliability
If IC area is enlarged to compensate for voltage drops, then IC performance is improved, but area requirements increase
Solution Approach 1:
The patent applies parameter changes by modifying routing parameters such as wire width, via size, and material selection to reduce parasitic resistance. By changing these physical parameters, the system compensates for voltage drops without requiring increased IC area, thus maintaining performance while minimizing area expansion
3Reliability
If layout adjustments are made to reduce parasitic resistance, then IC performance is improved, but time requirements increase
Solution Approach 1:
The patent applies preliminary action by performing parasitic estimation and IR drop analysis before final layout completion. This allows most optimizations to be made in advance, reducing the need for time-consuming iterative adjustments after layout implementation and accelerating the overall design process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains IC performance targets while minimizing time and area requirements, ensuring efficient post-layout verification without repeated layout modifications.
Implementation Method 1
an extra voltage drop (e.g. IR drop, indicating the voltage drop due to the current (I) and the resistance (R)) caused by parasitic resistance/capacitance in middle-end of line (MEOL) or back-end of line (BEOL)
Implementation Method 2
an extra voltage drop (e.g. IR drop, indicating the voltage drop due to the current (I) and the resistance (R))
Data Source
AI summary
The present disclosure provides a method and a non-transitory computer-readable medium for arranging components within a semiconductor device. The method includes providing a plurality of electrical components in a pre-layout, generating a first layout by routing the plurality of electrical components, obtaining a first resistance between a power terminal of the first layout and a first terminal of a first electrical component in the first layout, comparing the first resistance and a first threshold, adjusting routing of the first layout such that the first resistance is less than the first threshold, and generating a tape out file for the semiconductor device according to the first layout.