Multi-layer IC Routing Tool Resolving Wiring Space Overcrowding
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Solution Overview
Problem
Current multi-layer integrated circuit design tools face challenges in efficiently routing nets across hierarchical blocks without overcrowding wiring space, while also meeting timing requirements and accommodating blockages in metal layer allocation.
Innovation Solution
A computer-implemented method for a multi-layer integrated circuit routing tool that creates cycle and repeater reach tables, prepares a working list of nets, extracts blocked areas, and creates blockages to route nets based on constraint classes, prioritizing nets by complexity and performing routing in parallel to improve efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If repeaters are installed everywhere to meet timing requirements, then timing constraints are satisfied, but wiring space becomes overcrowded and blockages are violated
Solution Approach 1:
The patent applies local quality by making blockage definitions specific to each metal layer and location. Different metal layers have different blockage configurations based on their specific routing requirements and timing constraints. This allows repeaters to be placed only where actually needed on specific layers rather than uniformly everywhere, satisfying timing requirements while preserving wiring space.
Solution Approach 2:
The patent performs preliminary action by pre-defining blockages for each metal layer before the routing process begins. These blockages encode the locations where repeaters cannot be placed, allowing the router to plan routes in advance that respect both timing constraints and physical placement limitations, avoiding overcrowding while meeting timing requirements.
2Device complexity
If hierarchical blocks are used to simplify complex semiconductor developments, then design complexity is reduced, but routing becomes more difficult due to blockages and timing constraints
Solution Approach 1:
The patent applies segmentation by dividing the routing problem into separate metal layer treatments. Each metal layer is analyzed and configured independently with its own blockage definitions and routing constraints. This segmentation allows the router to handle complex hierarchical designs by breaking down the overall routing task into manageable layer-specific subtasks, reducing routing difficulty while preserving the benefits of hierarchical block usage.
Solution Approach 2:
The patent introduces a new dimension by adding metal layer specificity to blockage definitions. Instead of treating blockages as two-dimensional constraints, the invention extends blockage definitions to include metal layer information, creating a three-dimensional routing space (x, y, layer). This additional dimension allows nets to route around blockages by switching between metal layers, making routing easier in hierarchical designs while maintaining design complexity benefits.
3Area of stationary object
If thin wires are routed over blocks requiring repeaters, then wiring space is utilized, but repeaters must be placed outside blocks extending net length and violating constraints
Solution Approach 1:
The patent performs preliminary action by pre-defining blockages that extend over blocks requiring repeaters. This prevents the router from placing thin wires over these blocks in the first place, avoiding the need to place repeaters outside blocks. The blockages are established before routing, ensuring that net length constraints are satisfied while still utilizing wiring space effectively on appropriate metal layers.
Solution Approach 2:
The patent uses metal layer blockages as an intermediary mechanism to mediate between wiring space utilization and net length constraints. The blockages act as a filtering element that guides the router to select appropriate metal layers and routing paths, ensuring that nets are routed in a way that satisfies both space utilization and constraint requirements without violating net length specifications.
Data Source
AI summary
A computer implemented method for a multi-layer integrated circuit routing tool connecting sources with nets to sinks in a hierarchical multi-layer integrated circuit design environment, the method including creating a cycle reach table containing a first set of information parameters for two dimensional nets per metal layer combination, creating a repeater reach table containing a second set of information parameters per constraint class, preparing a working list of nets, preparing a list of blocks larger than repeater reach dimensions, connecting a source pin to a sink pin on preassigned metal layers, by routing the net based on the given constraint class.