IC Routing Zone Decomposition for Double Patterning

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Solution Overview

Problem

Integrated circuit (IC) designs utilizing double patterning technology (DPT) face inefficiencies due to routing jogs, which often lead to odd cycles that degrade routing efficiency and require complex stitch-aware routing tools, making it difficult to implement additional route patterns for jogging functions.

Innovation Solution

Designating a portion of a filler cell as a routing zone in the IC, ensuring routes placed within this zone are decomposable with others outside, and maintaining a critical distance from the zone's edge to avoid design rule check errors, thereby simplifying the implementation of jogging functions without needing stitch-aware tools.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If routing jogs are used to improve routing efficiency, then routing efficiency improves, but odd cycles are created that are not decomposable by DPT

Engineering Contradiction:
Improverouting efficiencyVSAvoiddecomposability by DPT
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The routing problem is segmented into two separate routing patterns (first and second route patterns) that are assigned to different masks. By dividing the routing into orthogonal segments (horizontal and vertical), the method enables routing jogs while maintaining DPT decomposability through the even cycle structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention introduces a new dimension to routing by implementing stitching between different route patterns. Routes can transition from one pattern to another through vertically or horizontally oriented stitching segments, enabling complex routing paths with jogs while maintaining decomposability through the two-mask DPT approach.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If additional route patterns are added to enable jogging function, then routing efficiency improves, but device complexity increases due to need for stitch-aware routing tools

Engineering Contradiction:
Improverouting efficiencyVSAvoidrouting tool complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The first and second route patterns serve multiple functions: they provide the jogging capability, maintain DPT decomposability, and enable stitching without requiring special stitch-aware tools. The orthogonal orientation of the two patterns allows them to work together universally for various routing scenarios.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The routing patterns are pre-configured with orthogonal orientations and stitching capabilities before the actual routing process. This preliminary structuring allows standard routing tools to handle the jogged routes without requiring complex stitch-aware functionality, as the decomposability is built into the pattern structure itself.

Inventive Principle:
Principle #10Preliminary action

3Area of stationary object

If routing zones are designated within filler cells, then chip area utilization improves, but manufacturing precision requirements increase to maintain critical distances

Engineering Contradiction:
Improvechip area utilizationVSAvoidcritical distance maintenance
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

Filler cells are transformed into routing zones with specific local qualities: they are designated to accept routes while maintaining critical distances from cell boundaries. This local modification allows efficient use of previously wasted filler cell areas without compromising the global DPT decomposability or manufacturing precision.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8719757B2Method to enhance double patterning routing efficiency
Publication Date: 2014.05.06 GLOBALFOUNDRIES US INC
  • US8719757B2 patent drawing
  • US8719757B2 patent drawing
  • US8719757B2 patent drawing

AI summary

A method for enabling jogging functionality in circuit designs utilizing DPT without the need for difficult to implement tools such as stitch-aware routing tools is disclosed. Embodiments include: displaying a user interface for generating an IC having a plurality of masks for a single layer; causing, at least in part, a presentation in the user interface of a cell placement of the IC that includes a filler cell; and designating a portion of the filler cell as a routing zone, the routing zone being configured such that routes placed in the routing zone are decomposable with other routes placed outside the filler cell.