IC Row Layout With Filler-Cell Routing for Mixed Cell Heights
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits face inefficiencies in routing due to wasted space between cells of different heights, leading to suboptimal use of area and potential signal stability issues.
Innovation Solution
The integration of routing wiring lines and special cells in rows of varying heights, utilizing wasted space to enhance routing efficiency and integrity by connecting logic cells across different height rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If cells of different heights are arranged in rows, then area utilization is improved by reducing wasted space, but routing complexity increases due to varying row heights
Solution Approach 1:
The patent introduces a vertical dimension variation by allowing rows to have different heights, transforming the traditional uniform grid layout into a multi-level structure. This dimensional change enables efficient use of whitespace by accommodating cells of different heights in the vertical direction, thereby improving area utilization without compromising routing capabilities.
Solution Approach 2:
The routing structure is segmented into multiple layers corresponding to different row heights. By dividing the routing space into distinct vertical segments, the patent enables independent routing paths for different height levels, which manages routing complexity while maintaining the benefits of variable row heights for area optimization.
2Productivity
If routing wiring lines are placed in rows with varying heights, then routing efficiency is improved by utilizing wasted space, but signal integrity may deteriorate due to increased routing length
Solution Approach 1:
The patent utilizes the vertical dimension created by varying row heights to place routing wiring lines in previously wasted spaces. This dimensional utilization allows routing paths to be optimized for efficiency without necessarily increasing horizontal routing length, thereby maintaining signal integrity while improving routing efficiency.
Solution Approach 2:
The patent creates multiple routing paths at different vertical levels (copies of routing functionality at different heights). This provides alternative routing options that can be selected based on signal integrity requirements, allowing the system to utilize wasted space for routing while maintaining the ability to choose optimal paths for signal-critical connections.
3Area of stationary object
If filler cells and decap cells are used to fill wasted space, then area utilization is improved, but device complexity increases due to additional cell types
Solution Approach 1:
The patent employs filler cells and decap cells that serve multiple functions: they fill wasted vertical space in variable-height rows, provide routing pathways, and in the case of decap cells, offer decoupling capacitance. This multi-functionality allows the same cell structures to address both area utilization and routing needs without proportionally increasing device complexity.
Solution Approach 2:
The filler cells and decap cells are strategically placed in wasted spaces to automatically serve dual purposes: filling structural gaps and providing routing channels. This self-service approach allows the cells to contribute to both area optimization and routing functionality without requiring additional dedicated structures, thereby limiting the increase in device complexity.
Data Source
AI summary
An integrated circuit includes a plurality of logic cells arranged in a first row extending in a first direction and including different types of active areas extending in the first direction, a filler cell arranged in a second row adjacent to the first row in a second direction orthogonal to the first direction and extending in the first direction, and a first routing wiring line arranged in the second row and connecting a first logic cell and a second logic cell apart from each other by a first distance among the plurality of logic cells. A height of the first row is different from a height of the second row.


