Save-restore Circuitry for Integrated Circuits with Scan Chain Adaptability
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Solution Overview
Problem
Existing power-saving methods for integrated circuits (ICs) face challenges in efficiently saving and restoring the operational state of design blocks, particularly due to issues with scan chains of varying lengths, which lead to inaccuracies and increased time and device area usage during the save-restore process.
Innovation Solution
The proposed solution involves a circuitry design where first memories with different numbers of cells store and retrieve data in a specific order, using a second memory to store data in a repeated sequence for scan chains of varying lengths, allowing for efficient state saving and restoration without the need for additional flip-flops or memory rearrangement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If scan chains of varying lengths are used to save design block state, then the save-restore process can accommodate different clock domain requirements, but inaccuracies occur in state restoration and additional time is required for memory rearrangement
Solution Approach 1:
The invention segments the memory structure into multiple banks, where each bank is dedicated to storing state information for a specific scan chain. This segmentation allows each memory bank to be independently sized and configured to match the length of its corresponding scan chain, eliminating the need for memory rearrangement and ensuring accurate state restoration without requiring additional flip-flops or complex control logic.
2Adaptability or versatility
If scan chains of varying lengths are used, then different clock domain requirements can be met, but increased device area is required for additional flip-flops or memory rearrangement structures
Solution Approach 1:
The invention segments the memory structure into multiple banks, where each bank is dedicated to storing state information for a specific scan chain. This segmentation allows each memory bank to be independently sized and configured to match the length of its corresponding scan chain, eliminating the need for memory rearrangement and ensuring accurate state restoration without requiring additional flip-flops or complex control logic.
3Loss of energy
If traditional save-restore methods are used with scan chains, then power consumption can be reduced during idle periods, but time is lost due to memory rearrangement and software execution
Solution Approach 1:
The invention performs preliminary organization of memory banks during the design phase, where each bank is pre-configured to correspond to a specific scan chain. This preliminary action eliminates the need for runtime memory rearrangement or software execution during state restoration, allowing the system to directly load saved state information into the appropriate scan chains, thereby minimizing restoration time while maintaining power-saving benefits.
Data Source
AI summary
In described examples, circuitry for saving and restoring a design block state includes first memories configured to receive, and store in different first memories in a first order, different portions of first data; and a second memory coupled to first memories. First memories with the most memory cells have N memory cells. First memories with fewer memory cells have M memory cells. When saving state, first data from different first memories is written in a second order to different corresponding regions of the second memory as second data. The second order repeats portions of the first data stored in sequentially first N mod M cells, determined using the first order, of corresponding first memories with fewer cells. When restoring state, second data is read from the second memory and stored, in the first order, in corresponding first memories; repeated portions are repeatedly stored in corresponding first memories with fewer cells.