2D Grid Division for IC Scan Logic Wiring Congestion
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Solution Overview
Problem
The increasing complexity of integrated circuits and high compression ratios in test compression lead to physical chip layout bottlenecks, causing wiring congestion and limiting the implementation of large compression ratios due to the large number of wires required for decompression and compression logic.
Innovation Solution
A method for dividing the testable logic of integrated circuits into a 2-dimensional grid, optimizing the placement of decompression and compression logic to reduce wire length and minimize congestion, by determining grid sizes and dividing regions based on side lengths to efficiently distribute XOR gates across the chip surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional global scan wiring is used to connect decompression logic to scan chains, then compression ratio can be achieved, but wiring congestion increases and chip area footprint increases
Solution Approach 1:
The patent divides the chip into multiple scan regions, each with its own decompression logic instance. This segmentation distributes the wiring load across different regions rather than having all wires converge to a single global decompression unit, thereby reducing wiring congestion while maintaining high compression ratios.
Solution Approach 2:
The patent transitions from a single global decompression point to a distributed two-dimensional grid of decompression logic instances across the chip. This spatial distribution across multiple dimensions reduces the density of wires in any single area, alleviating congestion problems.
2Quantity of substance
If more scan chains are used to increase compression ratio, then test data volume is reduced, but wire length and congestion around decompression logic increase
Solution Approach 1:
By dividing the chip into multiple scan regions with local decompression logic, the patent reduces the average wire length from the decompression logic to scan chains. Each region serves its local scan chains, eliminating the need for extremely long wires that would connect a single global decompression unit to all scan chains across the entire chip.
Solution Approach 2:
The patent places decompression logic locally within or near each scan region, optimizing the wiring distance for that specific region. This local placement reduces wire length and congestion in the area around decompression logic while still achieving overall high compression ratio across the entire chip.
3Productivity
If compression ratio exceeds 100x, then test efficiency is improved, but physical chip layout becomes a bottleneck due to extreme wiring congestion
Solution Approach 1:
The patent enables extreme compression ratios (100x and beyond) by segmenting the decompression logic into multiple distributed instances. This segmentation makes high compression ratios physically feasible by distributing the wiring load, preventing the extreme congestion that would occur with a single global decompression unit handling all scan chains.
Solution Approach 2:
By distributing decompression logic across a two-dimensional grid of scan regions rather than concentrating it in one location, the patent makes extreme compression ratios manufacturable. The spatial distribution across multiple dimensions allows wires to be routed more efficiently throughout the chip area, avoiding the bottlenecks that would prevent high compression ratios in traditional layouts.
Data Source
AI summary
Methods and computer-readable media for effecting physically efficient scans of integrated circuit designs may include selecting a two-dimensional grid size for exposure to the method, the two-dimensional grid having a size that includes a first side length, a second side length, and a number of flops. The method is performed to select a two-dimensional grid size that maximizes compression efficiency and limit wiring congestion on the IC. In one aspect, the method may be performed on each region of the grid that maintains one of a respective first side length and a respective second side length greater than one, including selecting a larger side, determining if the larger side is odd or even, and dividing the grid along the larger side into two regions each having a proportion of the flops. The scans of the resulting regions are efficient, and consequently facilitate integrated circuit design and subsequent manufacture.