Integrated Circuit Scan Test Control Signal Generation
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Solution Overview
Problem
Current scan test methods require external control signals for shift and capture phases, leading to resource inefficiencies and dead cycles due to the need for dedicated pins and limited channel speeds, especially in reduced pin count tests and event-driven direct memory access architectures.
Innovation Solution
The integration of a test pattern detection block, counter circuit, and control circuit within the integrated circuit to generate internal test mode control signals based on detected patterns, allowing for autonomous control of scan test phases and reducing reliance on external control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If external control signals are used for scan test phases, then the integrated circuit can be tested, but dedicated pins are required and channel speeds are limited
Solution Approach 1:
The patent extracts the test mode control signal generation function from external testers and relocates it inside the integrated circuit through a dedicated control circuit. This internal generation eliminates the need for external control pins, reducing pin requirements while maintaining full scan test functionality.
Solution Approach 2:
The integrated circuit becomes self-sufficient by internally generating its own test mode control signals through the control circuit, which detects scan chain patterns and automatically produces the necessary control signals. This self-service approach removes dependency on external pin-based control and enables faster testing.
2Productivity
If external control signals are used for scan testing, then scan phases can be controlled, but dead cycles occur and resource utilization is reduced
Solution Approach 1:
The control circuit continuously monitors the scan chain output for specific patterns and uses this feedback to dynamically control the test mode signal. This closed-loop feedback mechanism eliminates dead cycles by precisely timing control signal transitions to match actual scan chain state, maximizing resource utilization.
Solution Approach 2:
The control circuit is pre-configured with the logic to detect scan chain patterns and generate corresponding control signals in advance. This preliminary preparation allows the circuit to immediately respond to scan chain states without waiting for external control, eliminating idle time and improving resource utilization.
Data Source
AI summary
Various embodiments of methods and integrated circuits capable of generating a test mode control signal for a scan test through a scan chain (such as in an integrated circuit) are provided. The integrated circuit includes a test pattern detection block, a counter circuit, and a control circuit. The test pattern detection block is configured to receive a detection pattern and to detect a first pattern corresponding to a shift phase and a second pattern corresponding to a capture phase of a test pattern based on the detection pattern and to generate a trigger signal based upon the detection of the patterns. The control circuit generates and controls the test mode control signal based on the count states. The counter circuit is configured to generate one or more count states corresponding to one of the shift phase, the capture phase and the clock signal based on the detected pattern.