Integrated Circuit Seal Rings With Offset Gaps
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for packaging integrated circuits are complex and costly due to the need for conducting connections between dies, which also compromise the mechanical strength and reliability of the seal ring, as they often require connections to pass over the seal ring, reducing its effectiveness in preventing cracking and environmental damage.
Innovation Solution
The integration of inner and outer seal rings with offset gaps allows conductors to pass through the rings while maintaining mechanical strength, enabling efficient packaging and reducing manufacturing complexity by allowing conductors to pass through the side of the die, thus minimizing the need for external connections and pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conducting connections are made between multiple dies, then electrical connectivity between dies is achieved, but packaging complexity and manufacturing cost increase
Solution Approach 1:
The patent combines multiple dies into a single integrated structure with shared interconnect layers, eliminating the need for separate bonding wires or tabs for each die. The common interconnect structure allows multiple dies to share the same connection pathway to the package lead, reducing packaging complexity while maintaining electrical connectivity.
Solution Approach 2:
The interconnect structure serves multiple functions simultaneously: it provides electrical connection between dies, acts as a mechanical support structure, and enables thermal management. The shared interconnect layers perform both signal transmission and structural reinforcement, reducing the need for additional specialized components.
2Reliability
If conducting connections are made between multiple dies, then electrical connectivity is achieved, but manufacturing cost increases
Solution Approach 1:
By merging the interconnect structures of multiple dies into a single integrated system, the patent reduces the total number of manufacturing steps. The shared interconnect layers can be formed in a single deposition and patterning process rather than requiring separate processing for each die, significantly reducing manufacturing cost.
Solution Approach 2:
The patent performs preliminary integration of the interconnect structure during the semiconductor fabrication process itself, before final packaging. The interconnect layers are formed as part of the standard CMOS or bipolar fabrication sequence, eliminating the need for costly post-fabrication bonding operations.
3Strength
If seal ring is made continuous around the periphery, then mechanical strength and crack prevention are improved, but conductor passage capability deteriorates
Solution Approach 1:
The patent segments the seal ring into multiple discrete sections rather than forming a continuous ring. These segmented seal rings are positioned at strategic locations to provide mechanical reinforcement and crack prevention while leaving gaps that allow conductors to pass through. The segmentation maintains structural integrity while enabling conductor access.
Solution Approach 2:
The seal ring structure is optimized with different properties at different locations: dense and continuous in regions requiring maximum mechanical strength, and segmented or open in regions requiring conductor passage. This local variation in structure allows the seal ring to simultaneously provide mechanical protection and conductor access where needed.
4Reliability
If outer and inner seal rings are provided, then crack prevention capability is improved, but device complexity increases
Solution Approach 1:
The patent implements a nested seal ring structure where an inner seal ring is positioned within an outer seal ring, both surrounding the active circuit area. The inner seal ring provides reinforcement close to the sensitive circuitry, while the outer seal ring provides peripheral support. This nested arrangement maximizes crack prevention efficiency while using simple concentric geometries that are easy to fabricate.
Data Source
Figure 1a
Figure 1b
Figure 1c
AI summary
An integrated circuit and corresponding method of manufacture. The integrated circuit has' a' die (2) comprising: an'outer strengthening ring (32) around a periphery of the die, the outer ring having one or more gaps; and an inner strengthening ring (30) within the outer ring and around interior circuitry of the die, the inner ring having one or more gaps offset from the gaps of the outer ring. One or more conducting members (40) are electrically isolated from said rings and electrically connected to the interior circuitry, each member passing through a gap of the inner ring and through a gap of the outer ring.