Integrated Circuit Self-Test Using Processor Reuse
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Solution Overview
Problem
Existing integrated circuit testing methods, such as Logic Built-In Self-Test (LBIST), are inadequate as they do not test the on-chip test processing capability, leading to less robust testing and wasteful use of die space with dedicated logic for testing.
Innovation Solution
A self-test capable integrated circuit apparatus and method that includes a pattern generator, results store, self-test controller, and processor, where the processor cooperates with the self-test controller to self-test and evaluate results, eliminating the need for supplementary external logic and allowing simultaneous testing of scan channels and the processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated logic is provided for testing the logic to be scanned, then testing capability is improved, but die space is wasted
Solution Approach 1:
The processor is designed to perform dual functions: executing application code during normal operation and executing self-test code during testing modes. This eliminates the need for dedicated test processing logic, as the same processor resources are reused for both computational and testing purposes, thereby saving die space while maintaining testing capability
Solution Approach 2:
The system implements self-testing where the processor tests itself by executing test patterns generated by the pattern generator. The processor evaluates its own operation results through the scan channels and results store, eliminating the need for external dedicated test logic and achieving testing functionality through self-service mechanisms
2Reliability
If external logic is used for self-testing, then testing functionality is achieved, but device complexity increases
Solution Approach 1:
The invention extracts the test processing functionality from external dedicated logic and integrates it into the existing processor. By removing the need for separate external test logic and using only the pattern generator, scan channels, results store, and processor that already exist in the system, device complexity is reduced while maintaining self-testing functionality
Solution Approach 2:
Existing processor components are made multi-functional: the pattern generator serves both normal operation and test mode, the scan channels are used for both data processing and test pattern propagation, and the processor itself handles both application code and self-test code. This eliminates the need for additional external logic and reduces overall device complexity
Data Source
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AI summary
A self-test capable integrated circuit apparatus comprising a pattern generator (200), a results store (205) and testable logic (202, 204, 206). The testable logic (202, 204, 206) comprises a plurality of scan channels (202, 204), each of the channels (202, 204) being respectively coupled between the pattern generator (200) and the results store (205). A self-test controller (108) is arranged to supervise a self-test in respect of the testable logic (202, 204, 206) to generate self-test result data, the self-test result data being stored in the results store (205). A processing resource (206) is also coupled to the self-test controller(108) and coupled between the pattern generator (200) and the results store (205), the processing resource (206) being capable of evaluating the self-test result data stored in the results store (205). The testable logic (202, 204, 206) comprises the processing resource (206), which is arranged to cooperate with the self-test controller (118) so that the self-test is also in respect of the processing resource (206) and the processing resource (206) is able subsequent to the self-test to evaluate the self-test result data.