Master-Slave IC Synchronization for Capacitive Sensing Timing
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Solution Overview
Problem
Display driver integrated circuit chips in electronic devices often fail to synchronize properly, leading to artifacts and errors in capacitive sensing data, which affects the accuracy of input detection and display updating.
Innovation Solution
A system comprising a master IC chip and slave IC chips that generate and synchronize vertical and horizontal timing signals to drive sensor electrodes, ensuring synchronized capacitive frame acquisition and reducing timing mismatches that cause background capacitance and interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple IC chips are used to drive sensor electrodes for capacitive sensing, then the sensing coverage and functionality are improved, but timing synchronization between chips deteriorates, leading to artifacts and errors in sensing data
Solution Approach 1:
The system divides the sensing control into multiple independent IC chips (master and slave), where each chip manages a portion of the sensor electrodes. This segmentation allows parallel operation across multiple chips while maintaining individual chip autonomy, thus expanding sensing coverage without compromising timing synchronization through the master-slave architecture.
Solution Approach 2:
The master IC chip acts as an intermediary that generates and distributes timing signals (vertical timing signal VTS and horizontal timing signal HTS) to slave IC chips. This intermediary role ensures that all chips operate in synchronized timing cycles, preventing artifacts and errors that would arise from unsynchronized operation while allowing multiple chips to function simultaneously.
2Device complexity
If IC chips operate independently without synchronization, then device complexity is reduced, but measurement precision deteriorates due to background capacitance and interference
Solution Approach 1:
The master IC chip serves as a centralized intermediary that provides synchronized timing signals to all slave chips. This coordination mechanism ensures that sensing operations across multiple chips are temporally aligned, minimizing background capacitance and interference effects while maintaining relatively simple individual chip designs that rely on the master for timing coordination.
Solution Approach 2:
Each slave IC chip is designed to be self-contained and autonomous in its sensing operations, requiring minimal external control beyond the timing signals from the master chip. This self-service capability reduces overall system complexity while the synchronized timing ensures measurement precision by coordinating when each chip samples capacitive data.
3Ease of operation
If timing signals are not synchronized across IC chips, then ease of operation is improved, but manufacturing precision deteriorates due to timing mismatches causing background capacitance
Solution Approach 1:
The system segments timing signal generation and distribution functions, with the master IC chip responsible for generating standardized VTS and HTS signals that are distributed to slave chips. This segmentation allows each chip to operate independently with simple local control logic while ensuring precise timing alignment through the standardized signals from the master, thus maintaining both ease of operation and manufacturing precision.
4Device complexity
If multiple IC chips are implemented without a master-slave architecture, then device complexity is reduced, but reliability deteriorates due to lack of coordination causing artifacts in sensing data
Solution Approach 1:
The multi-chip system is segmented into one master IC chip and multiple slave IC chips, creating a hierarchical architecture that balances complexity and reliability. The master chip handles timing signal generation and coordination, while slave chips focus on localized sensing operations. This segmentation provides clear division of responsibilities, ensuring reliable synchronized operation without requiring complex peer-to-peer communication between all chips.
Solution Approach 2:
The master IC chip functions as an intermediary that coordinates timing signals across all slave chips, ensuring synchronized operation. This intermediary architecture provides a simple yet effective mechanism for maintaining reliability in multi-chip systems, as the master chip centralizes the coordination function and distributes synchronized timing signals to all slaves, preventing artifacts and data errors that would result from unsynchronized operation.
Data Source
AI summary
A system and method for synchronizing multiple integrated circuit (IC) chips for an input device having a display device integrated with a capacitive sensing device. A first one of the IC chips is a master IC chip and a second one of the IC chips is a slave IC chip. The master IC chip is configured to transmit synchronization signals to and from the slave IC chip, such that capacitive frames are acquired by each of the IC chips at substantially the same time, the initiation of the sensing signals is synchronized for each of the IC chips and the clock signals of the slave IC chips are synchronized with the clock signal of the master IC chip.