IC Anomaly Detection via Sensor-Based Classification
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Solution Overview
Problem
Current methods for improving quality in integrated circuit manufacturing, such as data feed forward, bi-variant and multi-variant analyses, and part-average testing, struggle to effectively identify and exclude outliers that may fail prematurely, leading to defects and reduced reliability in mission-critical applications like automotive and medical industries.
Innovation Solution
A computerized method for IC classification and outlier detection, which involves incorporating sensors into the IC design, simulating IC operations, and using hardware processors to collect sensor values, compare them to a classification scheme, and record classifications. This method allows for the identification of outliers and the reduction of test time by classifying ICs based on their sensor values and operational characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional testing methods (wafer tests, package tests, circuit tests) are used to detect defects, then defective ICs can be identified and discarded, but the methods fail to effectively identify outliers that may fail prematurely in mission-critical applications
Solution Approach 1:
The patent applies preliminary action by collecting and analyzing manufacturing data from multiple stages (wafer sort, package test, final circuit test) before the IC reaches the customer. This early detection and classification of outliers based on test parameter variations allows premature failure risks to be identified and addressed before deployment in mission-critical applications.
Solution Approach 2:
The patent implements feedback mechanisms by continuously monitoring test results across different manufacturing stages and using this data to adjust testing parameters and improve outlier detection. The system feeds back manufacturing statistics and test data to refine the classification of outliers, enhancing the ability to detect potential premature failures in subsequent production batches.
2Reliability
If data feed forward and multi-variant analyses are used to improve quality, then DPPM rates can be lowered, but the methods still cannot reliably identify outliers with high correlation to premature failures
Solution Approach 1:
The patent applies segmentation by dividing the analysis into distinct manufacturing stages (wafer sort, package test, final circuit test) and analyzing test parameters at each stage separately. This segmented approach allows the system to identify outliers based on parameter variations at specific stages without being overwhelmed by the complexity of analyzing all data simultaneously, while still achieving reliable premature failure prediction.
Solution Approach 2:
The patent uses parameter changes by monitoring variations in test parameters across different manufacturing stages and using these variations to identify outliers. The system tracks how test parameters change from one stage to another and uses these parameter changes to predict premature failures, simplifying the analysis while maintaining high reliability.
3Reliability
If part-average testing is used to identify well-centered parameters, then ICs with strongly on-spec parameters can be identified, but the method cannot effectively detect outliers that pass regular tests but fail in the field
Solution Approach 1:
The patent applies another dimension by adding a new dimension of analysis beyond traditional pass/fail testing. Instead of only checking whether parameters meet specifications, the system analyzes the distribution and variation of test parameters across multiple stages, identifying outliers based on their position in this additional dimensional space. This allows detection of ICs that pass regular tests but exhibit parameter patterns correlated with field failures.
Data Source
AI summary
A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.