Integrated Circuit Layout That Obscures Shared Diffusion Contacts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The threat of data theft and reverse engineering of integrated circuits poses a significant risk in the semiconductor industry, as stolen circuit designs can be used to produce and sell copied integrated circuits, disclose designs to competitors, or exploit vulnerabilities.
Innovation Solution
The integrated circuit design incorporates a unique arrangement of field effect transistors, where common source/drain diffusion regions are not connected to vertical terminal contact material, increasing the number of examination needles required to analyze individual transistors, thereby hindering reverse engineering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If common source/drain diffusion regions are connected to vertical terminal contact material, then ease of manufacturing and electrical connectivity are improved, but reverse engineering becomes easier and circuit design security deteriorates
Solution Approach 1:
The patent extracts the harmful information pathway by deliberately leaving common source/drain diffusion regions without vertical terminal contact material. This extraction removes the direct electrical access point that would enable reverse engineering, while the regions still serve their electrical function through alternative connection paths.
Solution Approach 2:
The patent applies preliminary anti-action by pre-emptively blocking access to transistor parameters through the absence of vertical terminal contact material. This preliminary measure prevents potential reverse engineering before it can occur, creating an inherent security barrier in the circuit design.
2Object-affected harmful factors
If the number of examination needles required to analyze transistors is increased, then circuit design security is improved, but measurement complexity and time increase
Solution Approach 1:
The patent moves the measurement problem from a two-dimensional surface contact approach to a more complex multi-dimensional measurement scenario. By removing vertical terminal contacts, it forces examination to occur through alternative paths involving multiple needles and three-dimensional positioning, significantly increasing measurement difficulty.
Solution Approach 2:
The patent creates asymmetry in the contact structure by selectively removing vertical terminal contact material from common source/drain regions while maintaining it for other terminals. This asymmetric design breaks the symmetry that would normally allow straightforward two-needle measurements, forcing more complex measurement approaches.
3Ease of operation
If vertical terminal contact material is present on all source/drain regions, then ease of operation and electrical connectivity are improved, but device complexity for security purposes deteriorates
Solution Approach 1:
The patent segments the terminal contact structure by applying vertical terminal contact material only to specific regions (certain source and drain regions) while deliberately omitting it from common source/drain diffusion regions. This segmentation creates a differentiated contact architecture that balances electrical connectivity with security.
Solution Approach 2:
The patent applies local quality by giving different contact properties to different regions of the device. Common source/drain regions have no vertical terminal contact material (enhancing security), while other source/drain regions maintain vertical contacts (ensuring connectivity). This localized differentiation optimizes both security and functionality.
Data Source
AI summary
Various embodiments describe an integrated circuit. The integrated circuit includes at least seven planar field effect transistors provided in a common substrate next to one another with a maximum feature size in accordance with a technology node of a maximum of 65 nm. Each field effect transistor of the at least seven planar field effect transistors includes a first source/drain diffusion region, a second source/drain diffusion region, a channel region between the drain diffusion region and the source diffusion region, and a gate terminal. Each field effect transistor of the at least seven planar field effect transistors includes at least one common source/drain diffusion region with another field effect transistor of the at least seven planar field effect transistors. The common source/drain diffusion regions are free of vertical terminal contact material.