Integrated Circuit Shield with Anti-Tamper Layer
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Solution Overview
Problem
Integrated circuits are vulnerable to reverse engineering and tampering, as adversaries can delayer the die to extract secret information by processing high-resolution images of the delayering process, which existing technologies fail to adequately protect against.
Innovation Solution
An anti-tamper layer is applied to the integrated circuit, forming shield dies that are bonded to the active die in a way that makes removal difficult without damaging the circuitry, using high-temperature materials like boron-nitride or diamond-like carbon, and positioning shield dies on both sides to protect against delayering attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the integrated circuit is left unprotected, then it is easy to delayer and analyze, but it becomes vulnerable to reverse engineering and information extraction
Solution Approach 1:
The patent applies a hard anti-tamper layer to the integrated circuit die before packaging, creating a protective barrier that prevents future delayering attacks. This preliminary protective action ensures that when the device is later subjected to reverse engineering attempts, the pre-applied hard layer will prevent successful delayering and information extraction.
Solution Approach 2:
The patent employs a composite structure combining the integrated circuit die with a hard anti-tamper layer made of materials such as diamond-like carbon, boron nitride, or silicon nitride. This composite material approach creates a device that maintains the electrical functionality of the original circuit while adding mechanical and chemical protection against delayering attacks.
2Reliability
If an anti-tamper layer is applied to protect the integrated circuit, then security against reverse engineering is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The hard anti-tamper layer is applied to the die surface before the die is packaged into its final housing. This timing in the manufacturing process allows the protective layer to be applied when the die is still accessible and can be integrated into existing die preparation workflows, minimizing disruption to overall manufacturing processes.
Solution Approach 2:
The patent specifies that the anti-tamper layer must have a hardness greater than 10 on the Mohs scale, which is a clear quantitative parameter that guides material selection and quality control. This parameter-based approach simplifies manufacturing by providing clear specifications for the protective layer rather than requiring complex performance testing.
3Reliability
If a hard anti-tamper layer is applied, then resistance to delayering attacks is improved, but the layer cannot be removed without damaging the circuitry
Solution Approach 1:
The patent intentionally designs the anti-tamper layer to be so strongly bonded to the die that removal of the layer would necessarily damage the underlying circuitry. This converts the potential harm of an irreversible protective layer into a benefit: any attempt to remove the layer for analysis or reverse engineering automatically destroys the circuit, thereby protecting the intellectual property through controlled destruction rather than through reversible protection.
Solution Approach 2:
The hard anti-tamper layer is applied in advance to prevent delayering attacks before they can occur. The layer's strong adhesion and hardness create a preliminary barrier that stops reverse engineering attempts at the outset, making it unnecessary to consider removal or reversal of the protective measure under normal circumstances.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents the extraction of secret information by making it impossible to remove the anti-tamper layer without damaging the active circuitry, thus enhancing the security of integrated circuits against reverse engineering and tampering.
Implementation Method 1
An anti-tamper layer is deposited on a silicon wafer without active circuitry
Implementation Method 2
The anti-tamper layer is etched away and a shield die is produced
Implementation Method 3
bonded in an oxide-to-oxide bond
Data Source
AI summary
An anti-tamper layer is applied to a blank wafer. The layered wafer is then diced into shield dies. A shield die is oxide-to-oxide bonded to the top of an active die such that removing the shield die will damage the active die. The shield die may be sized and positioned such that wirebond pads along one or more edges of the active die remain exposed. The exposed wirebond pads may be used to electrically connect, via wirebonds, the active die to a substrate. A second shield die may be attached to the bottom of the active die to help protect against the use of bottom-to-top delayering.