IC Internal Shield Verification Against Backside Attacks
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Solution Overview
Problem
Integrated circuits are vulnerable to backside attacks through the silicon substrate, which conventional shielding techniques fail to adequately protect, posing a serious threat to the security of sensitive data and circuit integrity.
Innovation Solution
Implementing an internal shield in the lowest technological layers of the IC device, comprising a mesh of conductive lines in the front-side part, and a verification circuit to detect and thwart backside attacks, along with the use of dummy transistors to enhance protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If passive shields are used to prevent viewing of the circuit, then attacks become more time-consuming, but breaches in the shield are not detected
Solution Approach 1:
The patent incorporates verification circuits that continuously monitor the integrity of shield structures and connected circuitries. When a breach or tampering event occurs, the verification circuit detects the anomaly and provides feedback by generating an error signal or alarm, enabling real-time detection of shield breaches that passive shields alone cannot identify.
Solution Approach 2:
The patent introduces verification circuits as intermediary components between the shield structures and the attack detection system. These verification circuits act as mediators that translate physical shield integrity states into detectable electrical signals, enabling the detection system to monitor shield breaches without directly observing the physical shield structure itself.
2Reliability
If active shields are used to disable the integrated circuit upon breach, then security is improved, but circumventing the shield remains theoretically possible though complex and time-consuming
Solution Approach 1:
The patent divides the protection system into segmented functional components: physical shield structures, verification circuits, and response mechanisms. This segmentation allows each component to perform its specific function independently, simplifying the overall design while maintaining high security. The modular approach reduces complexity compared to monolithic active shield designs.
Solution Approach 2:
The patent implements preliminary protective actions by pre-configuring shield structures and verification circuits during manufacturing. The verification circuits are pre-programmed with expected integrity states, and the shield structures are pre-positioned to cover critical areas. When an attack occurs, the system responds based on pre-established protocols, reducing the complexity of real-time decision-making.
3Object-affected harmful factors
If dense mesh shields are implemented to protect against front-side invasive attacks, then attack costs increase due to microscopic operations required, but the shield design becomes more complex
Solution Approach 1:
The patent applies local quality by concentrating dense mesh shield structures only in areas where sensitive circuitries are located, rather than uniformly across the entire IC device. The verification circuits are strategically positioned at critical junctions and entry points. This localized approach provides high security where needed while reducing overall design complexity and resource consumption in less critical areas.
Data Source
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AI summary
Embodiments of the invention provide a system for protecting an integrated circuit (IC) device from attacks, the IC device (100) comprising a substrate (102) having a front surface (20) and a back surface (21), the IC device further comprising a front side part (101) arranged on the front surface of the substrate (102) and stacked layers, at least one of said layers comprising a data layer comprising wire carrying data, the front side part having a front surface (13). The system comprises an internal shield (12) arranged in a layer located below said data layer and a verification circuit configured to check the integrity of at least one portion of the internal shield.