3D IC Shielding Structure for RF CMOS Signal Integrity
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Solution Overview
Problem
Integrated circuits face signal losses and nonlinearities due to electromagnetic interference from surrounding components and substrates, particularly in 3D semiconductor processing, which affects the performance of RF devices integrated with CMOS devices.
Innovation Solution
An electromagnetic shielding structure is implemented around transistors in integrated circuits, using electrically conductive or trap-rich materials to enclose the transistors and reduce interference, comprising a bottom, lateral sides, and optionally a top, to minimize signal propagation outside the normal signal path and enhance linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential or monolithic 3D semiconductor processing is used to co-integrate RF devices with CMOS devices, then device density is reduced and RF devices can be optimized with dissimilar processing, but undesirable signal losses and coupling increase due to interference from underlying devices and substrate
Solution Approach 1:
An electromagnetic shielding structure is introduced as an intermediary element between the RF device and the underlying CMOS devices/substrate. This shielding structure, comprising conductive or magnetic materials, acts as a mediator that blocks electromagnetic fields from propagating between the RF device and interfering components, thereby reducing signal losses and coupling while maintaining the 3D integrated configuration.
Solution Approach 2:
The electromagnetic shielding structure is segmented into multiple components including a bottom shielding layer in the substrate, lateral shielding walls, and a top shielding layer. This segmentation allows the shielding function to be distributed throughout the 3D structure, effectively blocking electromagnetic interference from multiple directions (bottom, sides, and top) while maintaining device density.
2Area of stationary object
If RF devices are stacked on top of CMOS devices in 3D integration, then area is reduced, but electromagnetic interference from surrounding components and substrate increases
Solution Approach 1:
The electromagnetic shielding structure is nested within the 3D integrated circuit architecture, with the bottom shielding layer integrated into the substrate, lateral shielding walls positioned around the RF device, and top shielding layer covering the RF device. This nested configuration provides comprehensive electromagnetic protection while maintaining the compact 3D stacked layout and minimizing chip area.
3Reliability
If shielding structures are added to protect transistors from electromagnetic interference, then signal linearity improves, but device complexity increases
Solution Approach 1:
The electromagnetic shielding structure serves multiple functions simultaneously: it blocks electromagnetic interference from the substrate and surrounding components, provides mechanical support for the 3D stacked configuration, and enables thermal management by conducting heat away from the RF device. This multi-functionality reduces the need for additional separate structures, thereby limiting the increase in device complexity while improving signal linearity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly reduces signal losses and cross-talk, improves signal linearity, and increases the signal-to-noise ratio, leading to higher circuit performance and improved electromagnetic shielding of transistors.
Implementation Method 1
an electromagnetic shielding structure shielding the second transistor from electromagnetic fields
Implementation Method 2
comprising a bottom underlying the second transistor and comprised in the host substrate, the first layer, if present, or the second layer, one or more lateral sides laterally bordering the second transistor, and optionally, a top overlaying the second transistor; wherein the bottom, each of the one or more lateral sides and, if present, the top each comprise at least one shielding element independently made up of either an electrically conductive material or a trap-rich material
Data Source
Figure 1~2b
Figure 3~4
Figure 5a~5d
AI summary
In a first aspect, the present invention relates to an integrated circuit, comprising: i. a host substrate (100); ii. optionally, a first layer (200) overlaying the host substrate (100), the first layer (200) optionally comprising a first transistor (210); iii. a second layer (500) overlaying the host substrate (100) and the first layer (200), if present, the second layer (500) comprising a second transistor (510); and iv. an electromagnetic shielding structure (600) shielding the second transistor (510) from electromagnetic fields, comprising - a bottom (610, 611) underlaying the second transistor (510) and comprised in the host substrate (100), the first layer (200), if present, or the second layer (500), - one or more lateral sides (620, 621, 622) laterally bordering the second transistor (510), and - optionally, a top (630) overlaying the second transistor (510); wherein the bottom (610, 611), each of the one or more lateral sides (620, 621, 622) and, if present, the top (630) each comprise at least one shielding element independently made up of either an electrically conductive material or a trap-rich material.