Integrated Circuit Shuffler for Side-Channel Attack Prevention
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Solution Overview
Problem
Semiconductor devices, such as smart cards, face security vulnerabilities due to key leakage during data transfer, particularly through side-channel attacks, which compromise encryption and decryption processes.
Innovation Solution
An integrated circuit device with a shuffler and logic unit that adjusts storage locations for data bits using a random number generator, ensuring secure encryption and decryption by varying storage locations even with the same address, thereby preventing side-channel attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is transferred using a fixed address mapping, then the operation is simple and fast, but the security is compromised due to predictable storage locations
Solution Approach 1:
The patent implements dynamic address mapping where the shuffler randomly selects target bit storages from registers based on a shuffle configuration. This dynamic selection changes the storage location mapping during operation, preventing side-channel attacks that rely on predictable memory access patterns. The shuffle configuration is adjusted when reset operation is performed, making the mapping dynamic rather than static.
Solution Approach 2:
The shuffler acts as an intermediary component between the processor core and the registers. It receives an address from the processor core, uses the shuffle configuration to select target bit storages, and stores data bits in these selected locations. This intermediary layer obscures the actual storage locations from the processor core, providing security while maintaining simple address interface.
2Reliability
If the same address always maps to the same register, then address management is simple, but security is weakened due to predictable data locations
Solution Approach 1:
The address-to-register mapping is made dynamic through the shuffle configuration. When a reset operation is performed, the shuffle configuration is adjusted, causing the same address to map to different registers or different bit storages within registers. This dynamic mapping prevents side-channel attacks that analyze predictable access patterns.
Solution Approach 2:
The shuffle configuration is prepared in advance through random selection of target bit storages during reset operations. This preliminary randomization ensures that when data transfer occurs, the mapping is already secured against prediction, without requiring complex real-time calculations during normal operation.
3Reliability
If data bits are stored in fixed positions within registers, then the storage process is efficient, but security is reduced due to predictable bit locations
Solution Approach 1:
The bit-level positions within registers are made dynamic through the shuffler's random selection process. The shuffler selects target bit storages from available bit storages in registers based on the shuffle configuration, ensuring that the same data bits are stored in different positions during different operations. This prevents bit-level side-channel attacks while maintaining efficient single-cycle storage through the shuffler's parallel selection capability.
Data Source
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AI summary
Described herein is an integrated circuit device includes a shuffler, a logic unit and registers each including two or more bit storages. The shuffler receives an address indicating one of the registers and data bits, selects target bit storages at which the data bits are to be stored from among bit storages of the registers depending on a shuffle configuration and the address, stores the data bits into the target bit storages, and transfers the data bits from the target bit storages depending on the shuffle configuration. The logic unit receives the data bits transferred from the shuffler and operates using the received data bits. The shuffle configuration is adjusted when a reset operation is performed.