Integrated Circuit Signal Line Parasitic Reduction
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Solution Overview
Problem
Existing micro-time measuring devices suffer from performance degradation due to parasitic resistance and capacitance in signal lines, which is not effectively addressed by integrating analog front-end circuits and time-to-digital converters in discrete circuit components.
Innovation Solution
An integrated circuit device is designed with an analog front-end circuit for waveform shaping and a time-to-digital converter, where the analog front-end circuit is positioned near the signal terminal and the time-to-digital converter is placed adjacent to it, allowing for optimal wiring and reducing parasitic effects, along with clock signal generation circuits synchronized with resonators to improve time-digital conversion performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If discrete separate circuit components are used for analog front-end circuit and time-to-digital converter, then ease of manufacture is improved, but measurement precision deteriorates due to parasitic resistance and capacitance in signal lines
Solution Approach 1:
The patent integrates the analog front-end circuit and time-to-digital converter into a single integrated circuit device, merging previously discrete components. This integration eliminates external signal lines between these circuits, thereby reducing parasitic resistance and capacitance while maintaining manufacturing feasibility through standard IC fabrication processes.
Solution Approach 2:
The patent introduces a dedicated signal line layout design that positions the analog front-end circuit adjacent to the second signal terminal and the time-to-digital converter adjacent to the analog front-end circuit. This intermediary positioning minimizes the length and complexity of signal lines, reducing parasitic effects without requiring external discrete components.
2Ease of operation
If signal lines are made longer to connect discrete components, then ease of operation is improved, but measurement precision deteriorates due to increased parasitic resistance and capacitance
Solution Approach 1:
The patent transitions from a discrete component layout requiring external connections to an integrated circuit layout where components are positioned in adjacent regions on the same chip. This dimensional reorganization eliminates the need for long external signal lines, reducing parasitic effects while maintaining operational simplicity through a unified device structure.
3Device complexity
If analog front-end circuit is positioned away from signal terminal, then device complexity is reduced, but measurement precision deteriorates due to increased parasitic effects in signal lines
Solution Approach 1:
The patent applies local quality by positioning the analog front-end circuit in a specific region adjacent to the second signal terminal, rather than distributing components uniformly. This localized positioning minimizes the signal line length from the terminal to the processing circuit, reducing parasitic effects in the critical signal path while maintaining overall device simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the performance of time-digital conversion by minimizing signal line parasitics and improving accuracy and resolution, while also enabling phase synchronization between clock signals, leading to improved measurement precision.
Implementation Method 1
a first oscillation circuit and outputs a first clock signal generated by the first oscillation circuit oscillating a first resonator, and a second clock signal generation circuit that includes a second oscillation circuit and outputs a second clock signal generated by the second oscillation circuit oscillating a second resonator
Data Source
AI summary
An integrated circuit device includes a terminal region in which a second signal terminal to which a second signal is input is disposed, an AFE circuit (analog front-end circuit) that performs waveform shaping of the second signal, and a time-to-digital converter that converts a time difference between a transition timing of a first signal and a transition timing of the second signal subjected to waveform shaping, to a digital value. When a direction from a first side of the integrated circuit device toward a second side facing the first side is set as a first direction, the AFE circuit is disposed on the first direction side of the terminal region, and the time-to-digital converter is disposed on at least one side of the first direction side of the AFE circuit and a side of a direction intersecting the first direction.