Integrated Circuit Signal Path Analysis for Suspect Feature Identification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional failure analysis techniques for integrated circuits are resource-intensive, expensive, and time-consuming, and there is a need for more efficient methods to improve yield, reliability, manufacturability, and system operation by better understanding interactions between complex hardware and software.
Innovation Solution
A method involving the selection of signal paths based on defined criteria, application of test patterns, identification of failing paths, mapping to features, and analysis to identify suspect features, which can be iteratively refined until user-defined criteria are met, using a computer system to implement these steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional failure analysis techniques are used to investigate root cause for specific failing chips, then detailed defect mechanism understanding is achieved, but the process becomes resource-intensive, expensive, and time-consuming
Solution Approach 1:
The patent performs preliminary actions by selecting and testing signal paths before physical failure analysis. Test patterns are applied to identify failing signal paths, and features are extracted in advance to create a dataset that guides subsequent physical analysis, reducing the need for extensive trial-and-error physical investigation
Solution Approach 2:
The patent creates a virtual model of the circuit behavior by mapping signal paths to features and analyzing test results computationally. This virtual analysis copies the essential characteristics of physical failure analysis, allowing detailed defect mechanism understanding to be achieved through data analysis rather than resource-intensive physical inspection
2Reliability
If comprehensive testing of all signal paths is performed, then complete defect detection is achieved, but the testing complexity and resource requirements increase significantly
Solution Approach 1:
The patent extracts only the necessary signal paths for testing by applying selection criteria that identify paths most likely to reveal defects. This extraction process filters out redundant paths, reducing testing complexity while maintaining defect detection completeness by focusing on critical signal paths
Solution Approach 2:
The patent segments the comprehensive testing task into manageable components: signal path selection, feature extraction, test pattern application, and result analysis. This segmentation allows complex testing to be performed systematically on subsets of signal paths rather than attempting to test all paths simultaneously, reducing overall testing complexity
Data Source
AI summary
A method for testing an integrated circuit and analyzing test data. The method includes: defining a set of signal path selection criteria; selecting a subset of signal paths of an integrated circuit design, the selecting signal paths meeting the selection criteria; identifying pattern observation points for each signal path of the subset of signal paths; selecting a set of features associated with the integrated circuit design; applying a set of test patterns to one or more integrated circuit chips; determining failing signal paths of the subset of signal paths for each integrated circuit chip; mapping failing signal paths of the subset of signal paths to the set of features to generate a correspondence between the failing signal paths and the features; and analyzing the correspondence and identifying suspect features of the set of features based on the analyzing.