IC Signal Synchronization via Variable Feedback Delay
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Solution Overview
Problem
Conventional methods for synchronizing output signals with a clock signal in integrated circuits, such as SDRAM, fail to individually optimize each component due to process variations, leading to suboptimal phase skew reduction and limited high-frequency operation.
Innovation Solution
A system and method that uses a phase detector and synchronization logic to incrementally alter the feedback delay in a Delay Locked Loop, monitoring the relative phase order of the clock and output signals, and ceases adjustments when a phase swap occurs, allowing for precise synchronization of each integrated circuit component.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a trimmable feedback delay is added to a DLL to account for input and output buffer delay, then the skew between external signals is reduced, but the device complexity increases and manufacturing testing time increases
Solution Approach 1:
The system performs self-calibration by automatically measuring its own signal skew and adjusting the delay elements accordingly. The calibration sequence measures the actual skew between input and output signals, and the system self-corrects by programming the delay elements to compensate for the measured skew, eliminating the need for external manual adjustment or complex testing infrastructure
Solution Approach 2:
The system implements a feedback mechanism where the measured skew information is used to adjust the delay elements. The calibration sequence measures the actual signal skew, feeds this information back to the delay control logic, and the delay elements are programmed to compensate for the measured skew, creating a closed-loop system that automatically optimizes signal timing
2Productivity
If feedback delay is set to average value for all components on a wafer, then manufacturing testing time is reduced, but the phase skew reduction becomes suboptimal due to process variations
Solution Approach 1:
The system applies local optimization by allowing each component to have its own individually calibrated delay settings based on its specific process variations. Each component measures its own skew characteristics and programs its delay elements accordingly, rather than applying a universal average setting to all components, thus optimizing performance for each local instance
Solution Approach 2:
The system dynamically adjusts the delay parameters based on measured skew characteristics. The calibration sequence measures the actual skew for each component and programs the delay elements with component-specific values, allowing the system to adapt to process variations by changing the delay parameters to match each component's actual performance
3Manufacturing precision
If extensive manufacturing testing is performed to individually optimize each component, then phase skew reduction is optimized, but the productivity and manufacturing time decrease
Solution Approach 1:
The system performs self-calibration during normal operation by automatically measuring its own signal skew and adjusting the delay elements accordingly. This self-service approach eliminates the need for extensive external manufacturing testing while achieving individual component optimization, as each component calibrates itself using its own operational signals
Solution Approach 2:
The system implements an automated feedback-based calibration process that measures actual signal skew during operation and adjusts delay elements accordingly. This feedback mechanism enables individual component optimization without requiring extensive manual testing, as the system automatically iterates to find the optimal delay settings based on real signal measurements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes phase skew between the clock and output signals, optimizing high-frequency performance by compensating for individual variations in delay, even among components on the same wafer, and reduces the need for extensive manufacturing testing.
Implementation Method 1
A DLL dynamically adjusts the delay of a variable delay line to reduce the phase skew between a synchronous signal being generated and the clock signal
Implementation Method 2
The relative phase order of the clock and output signals is monitored in the IC component
Data Source
AI summary
A synchronous output signal generated by an integrated circuit (IC) component is synchronized to an applied clock signal for each individual IC component. A variable feedback delay in the IC component is incrementally altered to alter the phase skew between the clock signal and the output signal. The relative phase order of the clock and output signals is monitored in the IC component. In response to detecting a swap in the relative phase order of the clock and output signals, the variable feedback delay ceases to be altered. In some embodiments, the IC component may be a SDRAM component.