Automated IC Simulation Bottleneck Identification

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Solution Overview

Problem

Analyzing complex integrated circuit (IC) designs to identify simulation performance bottlenecks and opportunities for improvement is a time-consuming manual process requiring senior engineering skills, hindering efficient design iteration and verification.

Innovation Solution

A method that automates the identification and resolution of simulation performance bottlenecks by generating reports during simulation, populating an electronic Design Activity Database, and modifying hardware description language (HDL) design files to indicate potential improvements, allowing for automated analysis and implementation of optimizations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If manual analysis is used to identify simulation performance bottlenecks, then analysis accuracy can be maintained, but productivity is reduced and turn-around-time increases

Engineering Contradiction:
Improveanalysis accuracyVSAvoidturn-around-time
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The system enables automated self-analysis of simulation performance by having the simulation tool automatically generate activity data, populate the database, identify bottlenecks, and suggest optimizations without requiring manual engineer intervention for each analysis cycle

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system transforms simulation performance analysis from a manual qualitative process to an automated quantitative process by collecting and analyzing numerical activity data from multiple simulation runs to objectively identify performance bottlenecks

Inventive Principle:
Principle #35Parameter changes

2Reliability

If manual analysis by senior engineers is performed, then quality of improvement identification is maintained, but device complexity and resource requirements increase

Engineering Contradiction:
Improvequality of improvement identificationVSAvoidresource requirements
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary automated analysis system that acts as a bridge between simulation execution and optimization implementation, using structured databases and algorithmic analysis to replace the need for senior engineer manual analysis while maintaining consistent quality

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system segments the complex analysis task into distinct automated components: simulation activity data collection, database population, bottleneck identification algorithms, and optimization suggestion generation, making the overall process more manageable and scalable

Inventive Principle:
Principle #1Segmentation

3Reliability

If frequent simulation iterations are performed to improve design, then design quality is improved, but cumulative simulation time increases

Engineering Contradiction:
Improvedesign qualityVSAvoidcumulative simulation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system implements feedback by automatically analyzing simulation results and generating actionable optimization suggestions that are fed back into the design process, enabling faster iteration cycles where each simulation run contributes to identifying specific improvements for the next iteration

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20220180033A1Identifying potential improvement opportunities for simulation performance of an integrated circuit design
Publication Date: 2022.06.09 SYNOPSYS INC
  • US20220180033A1 patent drawing
  • US20220180033A1 patent drawing
  • US20220180033A1 patent drawing

AI summary

Techniques for improved analysis and simulation of an IC design are disclosed. Simulation activity for an integrated circuit (IC) design is identified using one or more processors. One or more potential improvements to a simulation of the IC design are generated based on the simulation activity, the one or more potential improvements relating to at least one of signal activity or process activity, during simulation, reflected in the simulation activity. A hardware description language (HDL) design file corresponding to the IC design is modified to indicate the one or more potential improvements to the simulation.