Integrated Circuit Simulation Model Reduction via Device Merging
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Solution Overview
Problem
The increasing complexity of integrated circuits leads to longer simulation times due to large parasitic effects, which are difficult to model accurately without significant computational resources, resulting in unacceptable accuracy losses if parasitic elements are removed entirely.
Innovation Solution
The method involves reducing the number of discrete components by combining them into a combined device, using techniques such as reducing internal nodes to external terminal nodes, and applying criteria like RC time constants to simplify simulations, thereby reducing the number of calculations required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all discrete components and internal nodes are simulated, then simulation accuracy is maintained, but simulation time increases significantly
Solution Approach 1:
The patent combines multiple discrete components into equivalent combined devices. Specifically, it merges resistors, capacitors, and transistors into combined RC devices, combined transistor devices, and combined MOSFET devices with equivalent electrical characteristics. This reduces the total number of nodes in the circuit model from simulating every individual component to simulating only the combined devices, thereby significantly reducing simulation time while maintaining accuracy through equivalent circuit modeling.
Solution Approach 2:
The patent extracts and eliminates redundant internal nodes from the simulation model. By identifying and removing internal nodes that do not require full simulation detail, the system reduces the matrix size for numerical simulation. The extraction process removes unnecessary computational variables while preserving the essential electrical behavior through the equivalent combined device models.
2Productivity
If the number of discrete components is reduced, then simulation time decreases, but parasitic effect accuracy may be compromised
Solution Approach 1:
The patent applies local quality by differentiating between internal nodes and external terminal nodes in terms of simulation detail. Internal nodes are eliminated through combination, while external terminal nodes maintain their individual characteristics and are preserved in the simulation. This localized approach ensures that parasitic effects at critical external interfaces are accurately modeled while internal details are simplified through equivalent modeling.
Solution Approach 2:
The patent changes the modeling parameters by transitioning from individual component-level parameters to equivalent combined device parameters. Each combined device is characterized by equivalent electrical parameters (resistance, capacitance, transconductance) that represent the collective behavior of the original discrete components. This parameter transformation maintains the accuracy of parasitic effect modeling at the terminal level while reducing computational complexity.
3Device complexity
If internal nodes are eliminated, then matrix size is reduced, but modeling complexity increases
Solution Approach 1:
The patent segments the circuit modeling process into distinct phases: identification of combinable components, formation of equivalent combined devices, and preservation of essential terminal characteristics. This segmentation allows systematic reduction of internal nodes while maintaining external behavior accuracy. The structured approach divides the complex task of model reduction into manageable steps that preserve essential electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces simulation time, allowing for faster development cycles and maintaining simulation accuracy by modeling combined devices instead of individual components, thus addressing the complexity challenge of modern integrated circuits.
Implementation Method 1
Each of these devices has internal resistances and capacitances, which can at least partially be modeled with using the RC time constant (π=RC)
Data Source
AI summary
The time to test integrated circuits is increasing as a function of the complexity of integrated circuits and processes used to fabricate the integrated circuits. Embodiments of this disclosure include systems and methods for reducing the time to integrated circuits by reducing the number of devices individually modeled. Embodiments can reduce the number of modeled devices by combining two or more devices into a single combined device that models all discrete devices, but in a reduced form.