IC Simulation Speed via Scan Enable Signal Logic
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Solution Overview
Problem
Current compiled code simulators for IC chip testing become slow as the number of test patterns required increases with circuit size, and deep sub-micron technology introduces more failure mechanisms, necessitating improved speed in fault model simulation.
Innovation Solution
A computer-implemented method and apparatus that trace paths through combinational logic in an IC chip design, create and modify instruction sets to conditionally propagate signals based on the scan enable signal, and store these sets to optimize simulation by avoiding unnecessary signal propagation through mission paths when the scan enable signal is active.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of test patterns increases to achieve high fault coverage in deep sub-micron technology, then the testing completeness improves, but the simulation speed deteriorates
Solution Approach 1:
The patent extracts and removes unnecessary signal propagation operations from the simulation process. When the scan enable signal is active, the simulator eliminates propagation through mission paths (combinational logic portions) since these paths are not used during scan operations. This extraction of unnecessary computations directly addresses the contradiction by reducing simulation workload while maintaining complete fault coverage testing capability.
2Reliability
If signal propagation through combinational logic is always performed during test operations, then complete circuit behavior is simulated, but unnecessary computations reduce simulation efficiency
Solution Approach 1:
The patent implements dynamic adaptation of the simulation process based on the state of the scan enable signal. The simulator dynamically determines whether to propagate signals through combinational logic portions based on whether scan operations are in progress. When scan enable is active, propagation through mission paths is dynamically disabled. This dynamic approach maintains simulation accuracy when needed while maximizing efficiency during scan operations, directly resolving the contradiction between reliability and productivity.
Data Source
AI summary
A computer is programmed to prepare a computer program for simulating operation of an integrated circuit (IC) chip, in order to test scan circuitry therein. The computer is programmed to trace a path through combinational logic in a design of the IC chip, starting from an output port of a first scan cell and ending in an input port of a second scan cell. If the first and second scan cells receive a common scan enable signal, then the computer generates at least a portion of the computer program, i.e. software to perform simulation of propagating a signal through the path conditionally, for example when the common scan enable signal is inactive and alternatively to skip performing simulation when the common scan enable signal is active. The computer stores the portion of the computer program in memory, for use with other such portions of the computer program.