Augmented IC Simulation Model Switching Combinational Logic Clouds
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Solution Overview
Problem
The increasing complexity and size of integrated circuit (IC) designs require significant computational resources and time for verification, with current simulation methods often wasting resources by simulating combinational logic clouds during scan-in or scan-out operations when their outputs are ignored, and failing to perform ATPG tests correctly if these clouds are not simulated.
Innovation Solution
An augmented simulation model is created by inserting a switch between the output of a scan cell and the input of a combinational logic cloud, controlled by a simulation enable signal, allowing the verification test-bench to selectively turn off the simulation of combinational logic clouds during scan-in or scan-out operations, thereby avoiding unnecessary computation and ensuring ATPG patterns can be correctly simulated.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If combinational logic clouds are simulated during scan-in or scan-out operations, then ATPG tests can be correctly performed, but computational resources are wasted and simulation time increases
Solution Approach 1:
The patent applies dynamics by making the simulation of combinational logic clouds conditional rather than static. A control signal dynamically enables or disables the simulation of combinational logic clouds based on the operational mode (scan-in/scan-out versus normal operation). This allows the system to adapt its computational behavior to the current verification phase, simulating logic clouds only when necessary for ATPG tests and skipping them during scan operations where their outputs are ignored.
Solution Approach 2:
The patent applies local quality by selectively applying different simulation treatments to different parts of the circuit based on their functional context. Specifically, combinational logic clouds are simulated with full accuracy only in regions and time periods where their outputs are needed (during ATPG pattern generation), while being excluded from simulation in scan chain regions during scan-in/scan-out operations. This localized approach optimizes resource allocation by focusing computational effort only where it impacts verification accuracy.
2Reliability
If combinational logic clouds are simulated during scan-in or scan-out operations, then complete circuit behavior is captured, but computational resources are wasted
Solution Approach 1:
The patent applies partial action by performing simulation only to the extent necessary for verification. During scan-in and scan-out operations, the simulation of combinational logic clouds is partially disabled since their outputs are ignored in these modes. The control signal ensures that simulation resources are allocated partially (only to essential circuit elements) rather than fully (to all elements), thereby reducing computational resource consumption while maintaining verification completeness for the aspects that matter.
Solution Approach 2:
The patent applies the extraction principle by removing the unnecessary simulation component (combinational logic cloud simulation) from the verification process during specific operations. By extracting this computational burden from the simulation model during scan-in/scan-out operations, the system eliminates wasted computational resources while retaining the essential simulation capabilities needed for accurate verification during other operational modes.
3Productivity
If an augmented simulation model with switches is inserted, then simulation performance is improved, but device complexity increases
Solution Approach 1:
The patent applies the intermediary principle by introducing control signals as mediator elements between the verification test-bench and the simulation model. These control signals act as intermediaries that carry information about the current operational mode (scan-in, scan-out, or normal operation) and use this information to dynamically control whether combinational logic clouds are simulated. This intermediary layer enables intelligent resource management without requiring fundamental changes to the simulation engine itself, thus improving productivity while managing complexity through a clean control interface.
Data Source
AI summary
An augmented simulation model can be created of an integrated circuit (IC) design by inserting a switch in a simulation model of the IC design between an output of a scan cell and an input of a combinational logic cloud. A simulation enable signal can be used to control the switch. Next, an IC design simulation environment can be generated based on the augmented simulation model. The IC design can be verified by using the IC design simulation environment. The simulation enable signal can be activated when the combinational logic cloud is desired to be simulated by the IC design simulation environment.