IC Simulator ESD Buffer Placement for Cross-Hierarchy Tie Nets
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Solution Overview
Problem
Conventional integrated circuit design techniques fail to effectively avoid electrostatic discharge (ESD) fail regions caused by cross-hierarchy tie nets, leading to potential damage and limiting the size of the final chip design due to conservative design schemes that ensure antenna diodes satisfy the ESD distance threshold.
Innovation Solution
A system and method that perform correct-by-construction operations in integrated circuit design, facilitating the exchange of component layout information between hierarchy levels to place antenna diodes with different polarities, and implementing ESD fail region mitigation operations such as placing an ESD buffer component between the input antenna diode and the ESD noise source to decouple it from direct connection, thereby avoiding ESD fail regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conservative design schemes are used to ensure antenna diodes satisfy the ESD distance threshold, then reliability is improved, but chip area increases and design compactness deteriorates
Solution Approach 1:
The invention performs preliminary connectivity analysis during the design phase to identify cross-hierarchy tie nets that could cause ESD events. By analyzing the netlist and determining diode connectivity to pins and nets in lower hierarchical levels before fabrication, the system can proactively place ESD buffers to prevent ESD events, rather than relying on conservative spacing rules that increase chip area.
Solution Approach 2:
The invention introduces ESD buffer components as intermediary elements between antenna diodes and cross-hierarchy tie nets. These buffers act as mediators that protect against ESD events by providing a controlled discharge path, allowing the design to achieve reliable ESD protection without requiring increased spacing between components, thus maintaining design compactness.
2Manufacturing precision
If connectivity analysis is performed across hierarchical levels to identify ESD risks, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The invention segments the connectivity analysis into hierarchical levels, analyzing connections between different levels (chip level, core level, unit level, RLM level) separately. This segmented approach allows the system to manage complex cross-hierarchy connections by breaking them down into manageable hierarchical segments, improving placement accuracy without overwhelming complexity.
Solution Approach 2:
The invention adds a hierarchical dimension to the connectivity analysis, examining connections not just within the same level but across multiple hierarchical levels. This dimensional approach to analyzing the netlist structure enables precise identification of cross-hierarchy tie nets that could cause ESD events, allowing accurate buffer placement while systematically managing the complexity through hierarchical organization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces or eliminates ESD fail regions, allowing for more compact integrated circuit designs without density penalties, ensuring the avoidance of ESD events through precise connectivity analysis and buffer placement, thus optimizing chip design without trial-and-error iterations.
Implementation Method 1
avoiding an electrostatic discharge (ESD) region in an integrated circuit (IC)... determine an ESD fail region mitigation operation configured to avoid establishing the ESD region
Data Source
AI summary
A system is configured to avoid establishing an electrostatic discharge (ESD) region in an integrated circuit (IC). The system includes a processor and memory storing an IC simulator. The IC simulator establishes an IC chip that is sub-divided into a plurality of hierarchical levels. The IC simulator further analyzes a first hierarchical level to determine first connectivity information indicating connectivity between the first hierarchical level and one or both of lower-level pins and lower-level nets of a targeted hierarchical level having a lower-level of hierarchy with respect to the first hierarchical level and analyzes the targeted hierarchical level to determine second connectivity information indicating diode connectivity to one or both high-level pins and higher-level nets included in the first hierarchical level. The IC simulator determines an ESD fail region mitigation operation configured to avoid establishing the ESD region based on the first connectivity information and the second connectivity information.