IC Configuration via Single-Node Voltage Ramp Encoding
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Solution Overview
Problem
Integrated circuits face limitations in configuration due to restrictions on input/output pins during reset, leading to inefficiencies in silicon area usage and limited configuration bits, as traditional methods require additional pins and external resistors that impact normal operation.
Innovation Solution
A method and apparatus that determine a multi-bit configuration value on a single node using voltage and time thresholds, reducing the need for multiple pins and allowing configuration before the integrated circuit exits reset mode, employing a voltage ramp generation circuit and resistor-capacitor networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional strap pads with external resistors are used for configuration, then configuration functionality is achieved, but silicon area and pin count increase
Solution Approach 1:
The patent combines multiple configuration bits into a single pin by encoding them in the rise time of a voltage signal. Instead of using separate pins for each configuration bit, the invention merges multiple configuration parameters into one signal transmission channel, thereby reducing the number of required pins and silicon area while maintaining full configuration functionality.
Solution Approach 2:
The invention changes the parameter used for configuration from static voltage levels (traditional digital logic levels) to dynamic temporal characteristics (rise time duration). By measuring how long it takes for a voltage to rise from one threshold to another, the system can encode multiple configuration bits in a single signal, reducing the need for multiple physical pins.
2Adaptability or versatility
If multiple strap pads are added to increase configuration bits, then configuration options increase, but packaging area and board area increase
Solution Approach 1:
The patent merges multiple configuration options into a single pin by using temporal encoding. Instead of requiring one pin per configuration bit, the invention uses the rise time characteristics of a single voltage signal to represent multiple configuration parameters, thereby reducing packaging area and board area while maintaining diverse configuration options.
3Area of stationary object
If I/O pins are reused for both configuration and normal operation, then pin count is reduced, but configuration reliability during reset is compromised
Solution Approach 1:
The invention performs configuration signal transmission during the reset period, which is the preliminary phase before normal operation begins. By utilizing the reset time to transmit rise time-based configuration signals, the system ensures that configuration is completed before the I/O pin is needed for normal operation, thereby maintaining both pin reuse and configuration reliability.
Solution Approach 2:
The patent replaces the traditional mechanical/electrical switching mechanism (external resistors pulling pins to specific logic levels) with a temporal measurement mechanism. Instead of using static voltage levels that require external resistors, the system uses dynamic voltage rise time measurement, which can be implemented internally without external components, improving reliability during reset.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a single node to provide multiple configuration bits, reducing pin requirements and silicon area, and allows for efficient configuration without reusing general-purpose input/output pins, thereby improving the configuration efficiency of integrated circuits.
Implementation Method 1
a voltage ramp generation circuit and resistor-capacitor networks
Data Source
AI summary
A method and apparatus configures an integrated circuit by determining a multi-bit configuration value on a single node. The multi-bit configuration value is determined by using at least a voltage level at the single node and also by detecting a time to reach a voltage threshold level at the single node, based on a voltage ramp generation circuit. The method and apparatus also includes configuring an operation mode of a circuit in the integrated circuit based on the determined multi-bit configuration value from the single node. Multi-bit configuration values may be obtained on multiple single nodes in an integrated circuit. In one example, a voltage level is employed in addition to a time to reach a voltage threshold level whereas in another example a current level on a single node is utilized in combination with detection of a time to reach a voltage threshold level.