Integrated Circuit Spacer Thickness Optimization
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Solution Overview
Problem
Current integrated circuit manufacturing methods fail to optimize spacer thickness for different types of MOS transistors, leading to increased bulk and decreased density in non-volatile memory areas, and rely on thermal oxidation which may not provide adequate insulation between capacitor electrodes.
Innovation Solution
A method is developed to manufacture integrated circuits with varying spacer thicknesses for high-voltage, floating-gate, and low-voltage MOS transistors, using a sequence of insulating and polysilicon layer deposition and etching steps to form spacers and capacitor electrodes, avoiding thermal oxidation for improved insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform spacer thickness is used for all MOS transistor types, then manufacturing process is simplified, but memory density decreases and circuit bulk increases
Solution Approach 1:
The patent segments the spacer formation process into multiple distinct steps: first forming initial spacers, then selectively removing them from NVM transistor regions, and finally forming second spacers only in HV and LV transistor regions. This segmentation allows different spacer configurations for different transistor types, optimizing memory density while maintaining manageable manufacturing complexity through systematic process division.
Solution Approach 2:
The patent performs preliminary actions by first forming spacers across all transistor regions, then selectively removing them from NVM areas before final spacer formation. This preliminary uniform spacer formation simplifies the overall process planning, while the subsequent selective removal and reformation allows optimization for specific transistor types without complicating the base process structure.
2Ease of manufacture
If thermal oxidation is used to form insulating layers, then manufacturing process is simplified, but electrical insulation between capacitor electrodes is inadequate
Solution Approach 1:
The patent changes the material parameter of the insulating layer from thermally oxidized silicon oxide to deposited silicon oxide. This parameter change enables adequate electrical insulation between capacitor electrodes, as deposited oxide provides superior insulating properties compared to thermal oxide, while maintaining compatibility with existing CMOS fabrication processes.
3Reliability
If thicker spacers are used for all transistors to ensure adequate insulation, then electrical reliability is improved, but memory density decreases
Solution Approach 1:
The patent applies local quality by providing different spacer configurations for different transistor types: NVM transistors have no spacers (maximizing density), HV transistors have second spacers (providing adequate insulation for high voltage), and LV transistors have both first and second spacers. This localized differentiation ensures each transistor type receives the appropriate insulation level without unnecessarily increasing bulk elsewhere in the circuit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for thinner spacers around NVM transistors, increasing memory density and ensuring adequate electrical insulation between capacitor electrodes without the need for thermal oxidation, thus optimizing transistor design and circuit density.
Implementation Method 1
depositing a second polysilicon layer
Implementation Method 2
forming a second electrode of capacitor CAPA at least partly resting on the first electrode by etching the second polysilicon layer
Data Source
AI summary
An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.