Modeling Spatial Correlations in Integrated Circuit Devices
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Solution Overview
Problem
As integrated circuit process technology advances to smaller nodes, intra-die and inter-die variations in semiconductor and logic circuits exhibit spatial correlations that are difficult to model effectively, leading to challenges in circuit design and yield improvement.
Innovation Solution
A computer-implemented method is introduced to model spatial correlations among integrated circuit devices by assigning physical coordinates and representing process or electric parameters as a sum of stochastic terms, simulating device formation, and obtaining statistical properties to accurately describe these correlations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional modeling approaches are used for integrated circuit devices, then the modeling process is simple, but the accuracy of capturing spatial correlations deteriorates
Solution Approach 1:
The patent transforms the modeling approach by changing parameters from independent device variations to spatially correlated variations. It introduces correlation length parameters and spatial frequency components to describe how device parameters vary across the wafer surface, enabling accurate representation of spatial correlations while maintaining manageable model complexity through parameterized functions.
Solution Approach 2:
The patent adds a spatial dimension to the modeling by incorporating wafer coordinates (x, y positions) and correlation lengths that describe spatial relationships. This dimensional extension allows the model to capture how device parameters correlate across different locations on the wafer, transforming a one-dimensional parameter variation model into a two-dimensional spatial correlation model.
2Productivity
If spatial correlations are not modeled, then the modeling process is straightforward, but circuit design and yield improvement suffer
Solution Approach 1:
The patent implements feedback by using measured device parameters from actual wafers to calibrate and validate the spatial correlation model. The model predictions are compared against measured data, and model parameters (such as correlation lengths and spatial frequency distributions) are adjusted to match observed spatial variation patterns, ensuring the model accurately reflects real manufacturing processes.
Solution Approach 2:
The patent performs preliminary action by establishing the spatial correlation model before circuit design and yield analysis. By pre-characterizing the spatial variation patterns of device parameters across wafers, the model enables designers to predict performance variations and optimize circuit designs in advance, rather than discovering issues during manufacturing or testing.
Data Source
AI summary
A computer-implemented method, computer system, and computer program for modeling spatial correlations among a set of devices. A method includes: assigning a set of physical coordinates to each device in the set of devices; representing one of a process parameter or an electric parameter for each device as a sum of at least two stochastic terms, wherein the at least two stochastic terms are chosen to satisfy the spatial correlations; simulating formation of the set of devices using the physical coordinates and the at least one of the process parameter or the electric parameter; and obtaining statistical properties of the set of devices from the simulation.