IC Packaging with Stacking Structure for Known-Good-Die Testing

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Solution Overview

Problem

Current integrated circuit packaging systems face challenges in miniaturization, high packaging density, and flexible stacking configurations, leading to inefficiencies and assembly defects due to limited input/output capabilities and the difficulty in testing individual die before assembly.

Innovation Solution

The proposed integrated circuit packaging system involves an integrated circuit die with an active and passive side, connected by an inner bond wire to a contact pad, which is then molded within a stacking structure that exposes the passive side and top side, forming a cavity, allowing for flexible stacking and improved testing reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional multi-chip modules are used to reduce board space, then packaging density is improved, but assembly process yield deteriorates due to inability to test individual die before assembly

Engineering Contradiction:
Improvepackaging densityVSAvoidassembly process yield
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent enables preliminary testing of individual die before they are assembled into multi-chip modules. By exposing bond pads on the die surface and providing test access structures, the system allows die to be tested individually for known-good-die identification prior to assembly, thereby improving assembly process yield while maintaining high packaging density

Inventive Principle:
Principle #10Preliminary action

2Reliability

If die are individually tested and assembled using known-good-die approach, then assembly process yield is improved, but manufacturing complexity increases

Engineering Contradiction:
Improveassembly process yieldVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the test structure with the functional circuitry of the die, integrating test access into the manufacturing process flow. This merging allows die to be tested during or after fabrication without requiring separate complex test equipment or additional assembly steps, thereby improving assembly process yield while minimizing manufacturing complexity

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If leaded packages are used for stacking, then packaging flexibility is improved, but input and output capabilities are limited

Engineering Contradiction:
Improvestacking flexibilityVSAvoidinput and output capabilities
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent transitions from traditional leaded package I/O to a wire bond-based I/O architecture. By using wire bonds extending from the die surface through the package, the system provides multiple input and output channels in a three-dimensional configuration, thereby increasing I/O capabilities while maintaining stacking flexibility through vertical package arrangements

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8481420B2Integrated circuit packaging system with lead frame stacking module and method of manufacture thereof
Publication Date: 2013.07.09 STATS CHIPPAC MANAGEMENT PTE LTD
  • US8481420B2 patent drawing
  • US8481420B2 patent drawing
  • US8481420B2 patent drawing

AI summary

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit die having an active side and a passive side; providing a contact pad having a top side oriented in a same direction as the passive side; connecting an inner bond wire to the contact pad and the integrated circuit die; and molding a stacking structure around the contact pad, the inner bond wire, and the integrated circuit die with the passive side and the top side exposed, and the stacking structure having a top structure surface on top and adjacent to or below the integrated circuit die, and a horizontal member under the integrated circuit die and forming a cavity.