3D IC Stacking via Ion Implantation Cleaving
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Solution Overview
Problem
Conventional chip stacking methods using mechanical backgrinding impart mechanical stress and result in substantial thickness variation and limited inter-layer connection density, which hinders the efficient stacking and interconnection of heterogeneous and non-uniform integrated circuit layers.
Innovation Solution
A method involving ion implantation through dielectric and conductive structures to define a cleave plane, followed by cleaving and bonding of substrates with planarization, allowing for the stacking of three-dimensional integrated circuit devices with reduced thickness variation and increased inter-layer connection density, using techniques such as hydrogen implantation and plasma-activated bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If mechanical backgrinding is used to thin semiconductor substrates, then substrate thickness is reduced, but mechanical stress increases and thickness variation becomes substantial
Solution Approach 1:
The patent replaces the mechanical backgrinding process with ion implantation followed by cleaving. Ions are implanted through dielectric and conductive structures to define a cleave plane, and the substrate is then cleaved at this plane to obtain a cleaved layer. This substitution eliminates the mechanical stress and thickness variation problems associated with backgrinding while achieving the desired thinning.
Solution Approach 2:
The patent changes the physical and chemical state of the substrate by implanting ions at controlled energies and doses to create a cleave plane at a specific depth. This allows precise control over the cleaved layer thickness and eliminates the thickness variation inherent in mechanical processes. The ion implantation parameters (energy, dose, temperature) are carefully controlled to achieve uniform thinning without mechanical stress.
2Productivity
If conventional stacking methods are used, then device integration is achieved, but inter-layer connection density is limited
Solution Approach 1:
The patent segments the substrate into multiple thin layers through controlled ion implantation and cleaving. By implanting ions at different locations and energies, multiple cleave planes can be defined, allowing the substrate to be divided into several thin layers that can be stacked. This segmentation enables higher inter-layer connection density compared to conventional single-layer stacking methods.
Solution Approach 2:
The patent transitions from planar 2D stacking to 3D vertical stacking by creating multiple thin layers through ion implantation and cleving. The ability to define cleave planes at different depths and orientations enables three-dimensional integration, significantly increasing inter-layer connection density and enabling heterogeneous device stacking in the vertical dimension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of high-density inter-layer connections, increased signal bandwidth, and reduced mechanical stress, facilitating the stacking of heterogeneous and non-uniform integrated circuit layers with improved thermal management and alignment.
Implementation Method 1
implanting ions through dielectric and conductive structures of a first substrate to define a cleave plane in the first substrate
Implementation Method 2
cleaving the first substrate at the cleave plane to obtain a cleaved layer including the dielectric and conductive structures
Implementation Method 3
depositing a planarization material over the at least one die
Data Source
AI summary
A stacked semiconductor device is formed by implanting ions through dielectric and conductive structures of a first substrate to define a cleave plane in the first substrate, cleaving the first substrate at the cleave plane to obtain a cleaved layer including the dielectric and conductive structures, bonding at least one die to the first substrate, the at least one die having a smaller width than a width of the first substrate, depositing a planarization material over the at least one die, planarizing the planarization material to form a planarized upper surface over the at least one die, and stacking a third substrate on the planarized upper surface.