Integrated Circuit Standard Cell Yield Optimization
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Solution Overview
Problem
As semiconductor devices are downscaled, manufacturing defects and yield reduction become significant challenges due to the complexity of integrating a large number of transistors in a small space, necessitating improved semiconductor process technology and design for manufacturing (DFM) to enhance yield and performance.
Innovation Solution
A method of designing integrated circuits (ICs) by swapping standard cells with equivalent cells that have higher yield characteristics, such as removing stepwise portions in active regions to simplify manufacturing, while maintaining the same function and layout footprint, thereby improving yield without compromising performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are downscaled to integrate more in a small space, then integration density increases, but manufacturing defects and yield reduction occur
Solution Approach 1:
The patent modifies geometric parameters of the standard cell layout, specifically changing the active region shape from stepped to rectangular, and adjusts transistor dimensions while maintaining the same footprint. These parameter changes optimize the layout for manufacturing processes, reducing defects and improving yield without sacrificing integration density.
Solution Approach 2:
The patent applies different layout configurations to different standard cells based on their specific requirements. By analyzing critical paths and selecting appropriate standard cell versions (with or without stepped active regions) for specific cells, the patent locally optimizes each cell's contribution to overall yield while maintaining system-level performance.
2Reliability
If complex layouts are used to maintain performance, then functionality is preserved, but manufacturing difficulty increases
Solution Approach 1:
Instead of optimizing standard cells for performance first and then dealing with manufacturing issues, the patent inverts the approach by preparing alternative standard cell versions with simplified layouts that are inherently more manufacturable. These alternative versions are then selectively applied in the design, reversing the traditional optimization sequence to prevent manufacturing problems before they arise.
Solution Approach 2:
The patent changes the active region geometry parameter from stepped to rectangular shape, and modifies transistor width and length parameters within acceptable ranges. These parameter changes simplify the manufacturing process by eliminating complex etching steps while maintaining the electrical performance characteristics needed for proper circuit operation.
3Speed
If standard cells with stepped active regions are used, then performance is optimized, but manufacturing yield decreases
Solution Approach 1:
The patent applies different active region configurations to different standard cells based on their functional requirements. Cells on critical paths that require high speed performance use stepped active regions, while non-critical cells use simplified rectangular active regions. This local differentiation optimizes overall yield without significantly compromising the performance of time-critical circuit paths.
Solution Approach 2:
Instead of applying stepped active regions to all standard cells (excessive action), the patent selectively applies them only where performance requires it (partial action). This selective application reduces the overall manufacturing complexity and defect rate while maintaining adequate performance for critical functions.
Data Source
AI summary
A method of designing an integrated circuit includes a processor receiving input data initially-defining the integrated circuit using a plurality of first standard cells designed to optimize a performance or yield characteristic. The processor substitutes at least one second standard cell designed to optimize a different performance or yield characteristic from that for which the first standard cells were optimized for a corresponding one of the first standard cells. The processor generates output data defining the integrated circuit including the second standard cell. The substituted second standard cell has the same function as the corresponding first standard cell for which it was substituted.