IC Startup Sequencing for Propagated Initial Conditions
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Solution Overview
Problem
Integrated circuits (ICs) with volatile storage circuits face challenges in initializing user design operations efficiently, as synchronously lifting reset signals across multiple ICs requires significant resources, especially in ICs with configurable circuits, leading to high consumption of user resources like look-up tables and routing multiplexers.
Innovation Solution
The IC employs a sequencing circuit to delay the start of user design execution until initial conditions are computed and propagated, where a first group of circuits is held at an initial state while a second group computes and propagates these conditions, allowing the first group to release and perform user-defined operations only when the second group reaches a final computed state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reset signals are synchronously lifted across ICs using buffer elements and pipeline elements, then the system achieves predictable coordinated operation, but configurable user resources such as look-up tables and routing multiplexers are consumed in large numbers
Solution Approach 1:
The patent divides the IC into two distinct groups of circuits: a first group whose outputs serve as inputs to a second group. This segmentation allows differential control of reset signal lifting, where the first group can be released earlier than the second group, avoiding the need for extensive buffering and routing resources across the entire IC.
Solution Approach 2:
The patent applies preliminary action by holding the first group of circuits at an initial state while the second group computes and propagates initial conditions. This preliminary holding phase ensures that when the second group is ready, the first group is already initialized and can immediately begin user-defined operations, eliminating the need for complex synchronous coordination resources.
2Reliability
If a large number of buffer elements and pipeline elements are added to synchronize reset signal lifting, then coordinated operation is achieved, but device complexity increases
Solution Approach 1:
By segmenting the circuitry into two groups with different reset release timing, the patent eliminates the need for complex buffer and pipeline elements that would otherwise be required to synchronize reset lifting across the entire IC. The segmentation itself provides the coordination mechanism.
Solution Approach 2:
Instead of using traditional synchronous reset lifting with extensive buffering, the patent inverts the approach by using asynchronous release with hierarchical dependency: the first group is released first and serves as input to the second group, which is released later. This inversion simplifies the overall device complexity.
3Adaptability or versatility
If configurable circuits are used to implement user designs, then adaptability is improved, but resource consumption during initialization increases
Solution Approach 1:
The patent applies preliminary action by pre-initializing the first group of configurable circuits while the second group computes initial conditions. This allows the first group to be ready for user-defined operations immediately when released, without consuming additional user resources during the initialization phase.
Solution Approach 2:
The first group of circuits serves itself by being held at an initial state and automatically readying for user-defined operations once the second group completes its computation. This self-service mechanism eliminates the need for additional user resources to manage initialization coordination.
Data Source
AI summary
For an integrated circuit (IC) that is designed to execute user defined operations after initialization, a sequencing circuitry in the IC that delays the start of the user design execution until a set of initial condition has been computed and propagated is provided. The sequencing holds the first group of circuits at an initial state while a second group of circuits computes and propagates a set of initial conditions based at least partly on the initial state of the first group of circuits. The circuits in the first group when being held disregard their inputs and do not change their outputs. The first group of circuits is released from its initial state after the second group of circuits has completed computation and propagation of the set of initial conditions. The circuits in the first group when released are freed to store or clock-in new inputs and produce new outputs in order to perform the user defined operations in conjunction with the second group of circuits.