Integrated Circuit Programmable Storage Cell Array Boot-Up Optimization
Solution Overview
Problem
The boot-up operation in integrated circuits with programmable storage cell arrays is time-consuming due to the need for repeated read operations across multiple programmable storage cell groups, which increases the time and current required for the memory device to complete the repair and start normal operations.
Innovation Solution
An integrated circuit design that includes a programmable storage cell array with validity determination units to assess program validity information, allowing for the skipping of read operations for invalid data, thereby reducing the number of necessary read operations and shortening the boot-up time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If repeated read operations are performed across multiple programmable storage cell groups during boot-up, then all repair information is reliably loaded, but the boot-up time and current consumption increase significantly
Solution Approach 1:
The patent applies preliminary action by performing a validity check on the first programmable storage cell group before executing repeated read operations on subsequent cell groups. The validity determination unit assesses whether the stored repair information is valid in advance, allowing the system to skip unnecessary repeated read operations and thereby reducing boot-up time while maintaining reliable loading of repair information when needed
2Reliability
If repeated read operations are performed across multiple programmable storage cell groups during boot-up, then all repair information is reliably loaded, but the current consumption increases
Solution Approach 1:
The validity check performed on the first programmable storage cell group serves as a preliminary action that determines whether subsequent repeated read operations are necessary. By validating the repair information upfront, the system avoids performing energy-consuming repeated read operations on cell groups 2 through N when the information is already valid, thus reducing current consumption during the boot-up process
3Loss of time
If validity determination unit is added to assess program validity information, then unnecessary read operations are skipped, but the device complexity increases
Solution Approach 1:
The validity determination unit is designed to work within the existing memory device architecture, utilizing the same read circuitry and control mechanisms already present for normal memory operations. This multi-functional approach allows the validity check to be performed using existing resources, minimizing the increase in device complexity while still achieving the benefit of skipping unnecessary read operations
Data Source
AI summary
An integrated circuit may include a first programmable storage cell group suitable for storing program validity information, second to N-th programmable storage cell groups suitable for storing a plurality of data, wherein N is an integer equal to or more than 3, and a validity determination unit suitable for determining whether the program validity information read from the first programmable storage cell group is valid or not so that read operations for the second to N-th programmable storage cell groups is performed or skipped based on the determined result.