Integrated Circuit Stress Detection Using Compact Models

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Solution Overview

Problem

Semiconductor circuits with adjacent patterns made from different materials experience stress due to differing thermal expansion coefficients, leading to defects like standby leakage currents and cracks, which existing technologies struggle to effectively detect and mitigate across the entire integrated circuit.

Innovation Solution

A method and computing system for detecting stress in integrated circuits by determining stress detection points, dividing regions, calculating areas of adjacent patterns, and applying a compact model to rapidly assess stress levels, allowing for full-chip stress simulation and relaxation through dummy pattern insertion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional stress detection methods are used, then stress can be detected at limited points, but the detection coverage and accuracy across the entire integrated circuit is insufficient

Engineering Contradiction:
Improvestress detection accuracyVSAvoiddetection system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The integrated circuit is divided into multiple divided regions, and stress detection is performed at multiple stress detection points distributed across these regions. This segmentation approach enables comprehensive stress coverage throughout the entire circuit while maintaining manageable computational complexity through localized analysis at each point.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A compact model is introduced as an intermediary computational tool that calculates stress levels based on geometric information of adjacent patterns. This compact model serves as a mediator between the physical stress phenomenon and the detection system, enabling accurate stress assessment without requiring complex direct measurement techniques.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If full-chip stress simulation is performed using traditional methods, then comprehensive stress analysis can be achieved, but the processing time is excessively long

Engineering Contradiction:
Improvestress analysis completenessVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The essential stress detection functionality is extracted from complex traditional simulation methods into a simplified compact model. This extracted model retains the core capability to assess stress levels accurately while removing unnecessary computational complexity, enabling rapid full-chip stress analysis without excessive processing time.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The approach changes the parameters used for stress calculation from complex physical simulations to geometric-based parameters (areas of adjacent patterns at divided regions). This parameter transformation enables the compact model to compute stress levels rapidly while maintaining reliability through comprehensive coverage of all stress detection points across the entire circuit.

Inventive Principle:
Principle #35Parameter changes

3Area of stationary object

If multiple stress detection points are analyzed throughout the whole region, then detection coverage is improved, but the computational complexity increases

Engineering Contradiction:
Improvedetection coverage areaVSAvoidcomputational complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The detection area is segmented into multiple divided regions with stress detection points distributed throughout. This segmentation enables comprehensive coverage of the entire integrated circuit while keeping computational complexity manageable by performing localized stress calculations at each discrete point using the compact model.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The compact model is applied repeatedly at multiple stress detection points across the entire circuit. This copying of the computational model to multiple locations enables comprehensive stress analysis throughout the whole region without proportionally increasing complexity, as each copy uses the same efficient calculation approach.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS9798849B2Methods of detecting stresses, methods of training compact models, methods of relaxing stresses, and computing systems
Publication Date: 2017.10.24 SAMSUNG ELECTRONICS CO LTD
  • US9798849B2 patent drawing
  • US9798849B2 patent drawing
  • US9798849B2 patent drawing

AI summary

A method of detecting stress of an integrated circuit including first and second patterns formed from different materials may comprise: determining one or more stress detection points of the first pattern; dividing a region including a first stress detection point of the one or more stress detection points into a plurality of divided regions; calculating areas of the second pattern at the divided regions; and/or detecting a stress level applied to the first stress detection point of the first pattern by the second pattern based on the areas of the second pattern at the divided regions.